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First, since the internal register is kept in CPU cycles (not RCP cycles), we need to double the value written via MTC0/DMTC0. Second, writing a count equal to compare would cause an infinite loop because the fault would be triggered while PC was on the instruction doing MTC0 itself, which would be then re-executed at the end of the exception. On real hardware, in general, when COUNT==COMPARE, the interrupt happens a few cycles later, enough for PC to move to other opcodes. Instead of trying to implement this, I've simply made sure that the interrupt happened after the opcode was executed rather than before. Also, since the internal counter is in CPU cycles, we make sure to only raise the CAUSE bit once.
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