Update ram.py

naclander · May 4, 2020 · 57b5c6a · 57b5c6a
1 parent 130a782
commit 57b5c6a
Showing 1 changed file with 9 additions and 11 deletions.
diff --git a/pyboy/core/ram.py b/pyboy/core/ram.py
@@ -17,20 +17,18 @@
 
 class RAM:
     def __init__(self, randomize=False):
-        typecode = "B"
-
-        self.internal_ram0 = array.array(typecode, [0] * (INTERNAL_RAM0))
-        self.non_io_internal_ram0 = array.array(typecode, [0] * (NON_IO_INTERNAL_RAM0))
-        self.io_ports = array.array(typecode, [0] * (IO_PORTS))
-        self.internal_ram1 = array.array(typecode, [0] * (INTERNAL_RAM1))
-        self.non_io_internal_ram1 = array.array(typecode, [0] * (NON_IO_INTERNAL_RAM1))
-        self.interrupt_register = array.array(typecode, [0] * (INTERRUPT_ENABLE_REGISTER))
+        self.internal_ram0 = array.array("B", [0] * (INTERNAL_RAM0))
+        self.non_io_internal_ram0 = array.array("B", [0] * (NON_IO_INTERNAL_RAM0))
+        self.io_ports = array.array("B", [0] * (IO_PORTS))
+        self.internal_ram1 = array.array("B", [0] * (INTERNAL_RAM1))
+        self.non_io_internal_ram1 = array.array("B", [0] * (NON_IO_INTERNAL_RAM1))
+        self.interrupt_register = array.array("B", [0] * (INTERRUPT_ENABLE_REGISTER))
 
         if randomize: # NOTE: In real life, the RAM is scrambled with random data on boot.
-            for a in (self.internal_ram0, self.non_io_internal_ram0, self.io_ports, self.internal_ram1,
+            for mem in (self.internal_ram0, self.non_io_internal_ram0, self.io_ports, self.internal_ram1,
                       self.non_io_internal_ram1, self.interrupt_register):
-                for i in range(len(a)):
-                    a[i] = random.getrandbits(8)
+                for i in range(len(mem)):
+                    mem[i] = random.getrandbits(8)
 
     def save_state(self, f):
         for n in range(INTERNAL_RAM0):