Collect escape ids in Identifier, strip escape ids from escaping char… (

#5)

* Collect escape ids in Identifier, strip escape ids from escaping characters, store escaping as a property

* update workflows

* Testing with new Identifiers. Updating README

* fix coverage

.github/workflows/build.yml

@@ -19,7 +19,7 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
       with:
         submodules: true
     # install dependencies

.github/workflows/codeql-analysis.yml

@@ -38,7 +38,7 @@ jobs:
 
     steps:
     - name: Checkout repository
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4
       with:
         fetch-depth: 0
         submodules: true

.github/workflows/coverage.yml

@@ -19,7 +19,7 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
       with:
         fetch-depth: 0
         submodules: true

.github/workflows/reuse.yml

@@ -10,6 +10,6 @@ jobs:
   test:
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
     - name: REUSE Compliance Check
       uses: fsfe/reuse-action@v2

.github/workflows/valgrind.yml

@@ -19,7 +19,7 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
       with:
         fetch-depth: 0
         submodules: true

README.md

@@ -111,19 +111,21 @@ As ordering of verilog modules in single or across multiple files is not preknow
 
 ## Callbacks
 
-Stuctures (Net, Port, Expression) details constructed by following callbacks can be found in [VerilogType.h](https://github.com/najaeda/naja-verilog/blob/main/src/VerilogTypes.h) header.
+Stuctures (Identifier, Net, Port, Expression) details constructed by following callbacks can be found in [VerilogType.h](https://github.com/najaeda/naja-verilog/blob/main/src/VerilogTypes.h) header.
+
+An Identifier is a struct that holds the unescaped string. It also includes a boolean flag indicating whether the collected identifier was escaped or not.
 
 ### Callbacks for Module
 
 #### Starting a Module
 
 ```c++
-void startModule(const std::string& name);
+void startModule(const naja::verilog::Identifier& module);
 ```
 
-This callback is invoked when a module declaration begins. It receives the name of the module as an argument.
+This callback is invoked when a module declaration begins. It receives the identifier of the module as an argument.
 
-For instance, the callback is called with **name="foo"** for the Verilog module declaration below:
+For instance, the callback is called with **identifier:{name_="foo",escaped_=false}** for the Verilog module declaration below:
 
 ```verilog
 module foo;
@@ -148,15 +150,15 @@ endmodule //foo
 #### Simple Port Declaration in Module Interface
 
 ```c++
-void moduleInterfaceSimplePort(const std::string& name)
+void moduleInterfaceSimplePort(const naja::verilog::Identifier& port)
 ```
 
-Triggered when a module uses a simple declaration (only the port name) for ports. It will be called multiple times depending on the number of ports declared.
+Triggered when a module uses a simple declaration (only the port identifier) for ports. It will be called multiple times depending on the number of ports declared.
 
-For example, it is called with **name="a", name="b", and name="c"** for:
+For example, it is called with **identifier.name_="a", identifier.{name_="b@", escaped_=true}, and identifier.name_="c"** for:
 
 ```verilog
-module foo(a, b, c);
+module foo(a, \b@ , c);
 ```
 
 #### Port details in module implementation
@@ -170,14 +172,14 @@ void moduleImplementationPort(const Port& port)
 is called for each port listed in the implementation section of a module.
 
 ```verilog
-module foo(a, b, c);
+module foo(\a# , b, c);
 input a;
 output [3:0] b;
 inout c;
 //will invoke 3 times moduleImplementationPort with:
-//Port name_=a, direction=Input, isBus()=true, range_.msb_=3, range_.lsb_=0
-//Port name_=b, direction=Output, isBus()=true, range_.msb_=0, range_.lsb_=3
-//Port name_=c, direction=InOut, isBus()=false
+//Port identifier_={a#,true}, direction=Input, isBus()=true, range_.msb_=3, range_.lsb_=0
+//Port identifier_={b,false}, direction=Output, isBus()=true, range_.msb_=0, range_.lsb_=3
+//Port identifier_={c,false}, direction=InOut, isBus()=false
 ```
 
 #### Port complete declaration in Module interface
@@ -191,9 +193,9 @@ Invoked for a complete interface port declaration, detailing port direction (inp
 ```verilog
 module foo(input[3:0] a, output[0:3] b, inout c);
 //will invoke 3 times moduleInterfaceCompletePort with:
-//Port name_=a, direction=Input, isBus()=true, range_.msb_=3, range_.lsb_=0
-//Port name_=b, direction=Output, isBus()=true, range_.msb_=0, range_.lsb_=3
-//Port name_=c, direction=InOut, isBus()=false
+//Port identifier_={a,false}, direction=Input, isBus()=true, range_.msb_=3, range_.lsb_=0
+//Port identifier_={b,false}, direction=Output, isBus()=true, range_.msb_=0, range_.lsb_=3
+//Port identifier_={c,false}, direction=InOut, isBus()=false
 ```
 
 ### Callbacks for Nets
@@ -224,20 +226,20 @@ Below are Verilog examples followed by pseudo C++ representations of the data st
 
 ```verilog
 assign n0 = n1;
-//identifiers = { {name_=n0, range_.valid_=false} }
+//identifiers = { {identifier_={n0,false}, range_.valid_=false} }
 //expressions = 
 // {
 //   { 
 //     value_.index()=naja::verilog::Expression::Type::IDENTIFIER
 //     with auto id=std::get<naja::verilog::Expression::Type::IDENTIFIER>(value_)
-//     id.name_="n1", id.range_.valid_=false
+//     id.identifier_={"n1",false}, id.range_.valid_=false
 //   } 
 // }
 ```
 
 ```verilog
 assign n1 = 1'b0;
-//identifiers = { {name_=n1, range_.valid_=false} }
+//identifiers = { {identifier_={n1,false}, range_.valid_=false} }
 //expressions = 
 // {
 //   { 
@@ -253,16 +255,16 @@ assign n1 = 1'b0;
 assign { n2[3:2], n2[1:0] } = { n0, n1, 2'h2 };
 //identifiers =
 // {
-//    { name_=n2, range_.valid_=true, range_.msb_=3, range_.lsb=3 },
-//    { name_=n2, range_.valid_=true, range_.msb_=1, range_.lsb=0 },
+//    { identifier_={n2,false}, range_.valid_=true, range_.msb_=3, range_.lsb=3 },
+//    { identifier_={n2,false}, range_.valid_=true, range_.msb_=1, range_.lsb=0 },
 // }
 //expressions = 
 // {
 //   { 
 //     value_.index()=naja::verilog::Expression::Type::CONCATENATION
 //     with auto concat=std::get<naja::verilog::Expression::Type::CONCATENATION>(value_)
-//     concat[0] is an Identifier name_=n0, range_.valid_=false
-//     concat[1] is an Identifier name_=n1, range_.valid_=false
+//     concat[0] is an Identifier identifier_={n0,false}, range_.valid_=false
+//     concat[1] is an Identifier identifier_={n1,false}, range_.valid_=false
 //     concat[2] is an NUMBER with:
 //     nb.base_=naja::verilog::BasedNumber::HEX
 //     nb.size_=2, nb.digits_="2"
@@ -275,10 +277,10 @@ assign { n2[3:2], n2[1:0] } = { n0, n1, 2'h2 };
 #### Starting Instantiation
 
 ```c++
-void startInstantiation(const std::string& modelName)
+void startInstantiation(const naja::verilog::Identifier& model)
 ```
 
-allows to collect module (used as a model) name for one or multiple instanciations. This method will collect `modelName=Model` for the two following declarations:
+allows to collect module (used as a model) name for one or multiple instanciations. This method will collect `model={Model,false}` for the two following declarations:
 
 ```verilog
 Model ins();
@@ -288,10 +290,10 @@ Model ins0(), ins1(), ins2();
 #### Adding an Instance
 
 ```c++
-void addInstance(const std::string& instanceName)
+void addInstance(const naja::verilog::Identifier& instance)
 ```
 
-will be called 3 times with `instanceName=ins1, ins2, ins3` for following declaration:
+will be called 3 times with `instance={ins1,false}, {ins2,false}, {ins3,false}` for following declaration:
 
 ```verilog
 Model ins(), ins2(), ins3();
@@ -310,23 +312,23 @@ is called at the conclusion of an instance declaration, it signals that all inst
 #### Named Port Connection
 
 ```c++
-void addInstanceConnection(const std::string& portName, const Expression& expression);
+void addInstanceConnection(const naja::verilog::Identifier& port, const Expression& expression);
 ```
 
 This function is called for each named port connection in an instance, capturing the relationship between the port and its connected net or expression.
 
 ```verilog
 mod1 inst2(.i0(net4[3:6]), .o0(net5));
 //addInstanceConnection is called 2 times with:
-//portName=i0
+//port=Identifier{"i0",false}
 //expression_.value_.index() = naja::verilog::Expression::Type::IDENTIFIER,
 //with auto id = std::get<naja::verilog::Expression::Type::IDENTIFIER>(expression.value_)
-//id.name_="net4", id.isBus=true, id.range_.msb_=3, is.range_.lsb_=6
+//id.identifier_={"net4",false}, id.isBus=true, id.range_.msb_=3, is.range_.lsb_=6
 //and:
-//portName=o0
+//port=Identifier{"o0",false}
 //expression_.value_.index() = naja::verilog::Expression::Type::IDENTIFIER,
 //with auto id = std::get<naja::verilog::Expression::Type::IDENTIFIER>(expression.value_)
-//id.name_="net5", id.isBus=false
+//id.identifier_={"net5",false}, id.isBus=false
 ```
 
 #### Ordered Port Connection
@@ -343,7 +345,7 @@ mod1 inst4(net4[7:10], {net0, net1, net2, net3});
 //portIndex=0
 //expression_.value_.index() = naja::verilog::Expression::Type::IDENTIFIER,
 //with auto id = std::get<naja::verilog::Expression::Type::IDENTIFIER>(expression.value_)
-//id.name_="net4", id.isBus=true, id.range_.msb_=7, is.range_.lsb_=10
+//id.identifier_={"net4",false}, id.isBus=true, id.range_.msb_=7, is.range_.lsb_=10
 //and:
 //portIndex=1
 //expression_.value_.index() = naja::verilog::Expression::Type::CONCATENATION,
@@ -354,7 +356,7 @@ mod1 inst4(net4[7:10], {net0, net1, net2, net3});
 ### Callback for Parameter Assignment
 
 ```c++
-void addParameterAssignment(const std::string& parameterName, const Expression& expression);
+void addParameterAssignment(const naja::verilog::Identifier& parameter, const Expression& expression);
 ```
 
 This callback function is designed to handle parameter assignments within module instantiations.
@@ -366,7 +368,7 @@ module test();
   ) ins();
 endmodule
 //addParameterAssignment is called one time with:
-//parameterName=PARAM0 and expression is an Identifier with name="VAL"
+//parameter={"PARAM0",false} and expression is a RangeIdentifier with name="VAL"
 ```
 
 <div align="right">[ <a href="#naja-verilog">↑ Back to top ↑</a> ]</div>

src/NajaVerilogSnippet.cpp

@@ -14,11 +14,11 @@ void commandLine() {
 
 class VerilogConstructorExample: public naja::verilog::VerilogConstructor {
   public:
-    void startModule(const std::string& name) override {
-      std::cout << "Construct Module: " << name << std::endl;
+    void startModule(const naja::verilog::Identifier& id) override {
+      std::cout << "Construct Module: " << id.getDescription() << std::endl;
     }
-    void moduleInterfaceSimplePort(const std::string& name) override {
-      std::cout << "Simple Port: " << name << std::endl;
+    void moduleInterfaceSimplePort(const naja::verilog::Identifier& port) override {
+      std::cout << "Simple Port: " << port.getString() << std::endl;
     }
     void moduleInterfaceCompletePort(const naja::verilog::Port& port) override {
       std::cout << "Complete Port: " << port.getString() << std::endl;
@@ -29,20 +29,20 @@ class VerilogConstructorExample: public naja::verilog::VerilogConstructor {
     void addNet(const naja::verilog::Net& net) override {
       std::cout << "Construct Net: " << net.getString() << std::endl;
     }
-    void startInstantiation(const std::string& modelName) override {
-      std::cout << "startInstantiation: " << modelName << std::endl;
+    void startInstantiation(const naja::verilog::Identifier& model) override {
+      std::cout << "startInstantiation: " << model.getString() << std::endl;
     }
-    void addInstance(const std::string& instanceName) override {
-      std::cout << "addInstance: " << instanceName << std::endl;
+    void addInstance(const naja::verilog::Identifier& instance) override {
+      std::cout << "addInstance: " << instance.getString() << std::endl;
     }
-    void addInstanceConnection(const std::string& portName, const naja::verilog::Expression& expression) override {
-      std::cout << "addInstanceConnection: " << portName << ": " << expression.getString() << std::endl;
+    void addInstanceConnection(const naja::verilog::Identifier& port, const naja::verilog::Expression& expression) override {
+      std::cout << "addInstanceConnection: " << port.getString() << ": " << expression.getString() << std::endl;
     }
     void endInstantiation() override {
       std::cout << "endInstantiation" << std::endl; 
     }
-    void addParameterAssignment(const std::string& parameterName, const naja::verilog::Expression& expression) override {
-      std::cout << "addParameterAssignment: " << parameterName << ": " <<  expression.getString() << std::endl;
+    void addParameterAssignment(const naja::verilog::Identifier& parameter, const naja::verilog::Expression& expression) override {
+      std::cout << "addParameterAssignment: " << parameter.getString() << ": " <<  expression.getString() << std::endl;
     }
     void endModule() override {
       std::cout << "endModule" << std::endl; 

src/VerilogConstructor.cpp

@@ -67,23 +67,23 @@ void VerilogConstructor::internalParse(std::istream &stream) {
   bool result = parser_->parse();
 }
 
-void VerilogConstructor::internalStartModule(const std::string& name) {
+void VerilogConstructor::internalStartModule(const naja::verilog::Identifier& id) {
   type_ = ModuleInterfaceType::Unknown;
-  startModule(name);
+  startModule(id);
 }
 
 void VerilogConstructor::internalEndModule() {
   endModule();
 }
 
-void VerilogConstructor::internalModuleInterfaceSimplePort(const std::string& name) {
+void VerilogConstructor::internalModuleInterfaceSimplePort(const naja::verilog::Identifier& id) {
   if (type_ == ModuleInterfaceType::Unknown) {
     type_ = ModuleInterfaceType::Port; 
   }
   if (type_ == ModuleInterfaceType::PortDeclaration) {
-    moduleInterfaceCompletePort(Port(name, lastDirection_, lastRange_));
+    moduleInterfaceCompletePort(Port(id, lastDirection_, lastRange_));
   } else {
-    moduleInterfaceSimplePort(name);
+    moduleInterfaceSimplePort(id);
   }
 }
 

src/VerilogConstructor.h

@@ -50,20 +50,20 @@ class VerilogConstructor {
     }
 
     //LCOV_EXCL_START
-    virtual void startModule(const std::string& name) {}
+    virtual void startModule(const naja::verilog::Identifier& id) {}
     //Simple Port declaration (only name), no range, no direction in module interface
-    virtual void moduleInterfaceSimplePort(const std::string& name) {}
+    virtual void moduleInterfaceSimplePort(const naja::verilog::Identifier& port) {}
     //Complete Port declaration in module interface
     virtual void moduleInterfaceCompletePort(const Port& port) {}
     virtual void moduleImplementationPort(const Port& port) {}
     virtual void addNet(const Net& net) {}
-    virtual void addAssign(const Identifiers& identifiers, const Expression& expression) {}
-    virtual void startInstantiation(const std::string& modelName) {}
-    virtual void addInstance(const std::string& instanceName) {}
-    virtual void addInstanceConnection(const std::string& portName, const Expression& expression) {}
+    virtual void addAssign(const RangeIdentifiers& identifiers, const Expression& expression) {}
+    virtual void startInstantiation(const naja::verilog::Identifier& model) {}
+    virtual void addInstance(const naja::verilog::Identifier& instance) {}
+    virtual void addInstanceConnection(const naja::verilog::Identifier& port, const Expression& expression) {}
     virtual void addOrderedInstanceConnection(size_t portIndex, const Expression& expression) {}
     virtual void endInstantiation() {}
-    virtual void addParameterAssignment(const std::string& parameterName, const Expression& expression) {}
+    virtual void addParameterAssignment(const naja::verilog::Identifier& parameter, const Expression& expression) {}
     virtual void endModule() {}
     //LCOV_EXCL_STOP
   private:
@@ -80,9 +80,9 @@ class VerilogConstructor {
           ModuleInterfaceTypeEnum typeEnum_;
     }; 
     void internalParse(std::istream& stream);
-    void internalStartModule(const std::string& name);
+    void internalStartModule(const naja::verilog::Identifier& id);
     void internalEndModule();
-    void internalModuleInterfaceSimplePort(const std::string& name);
+    void internalModuleInterfaceSimplePort(const naja::verilog::Identifier& id);
     void internalModuleInterfaceCompletePort(const Port& port);
     void internalModuleImplementationPort(const Port& port);