use correct method

najaeda · Apr 2, 2024 · 89ce40b · 89ce40b
1 parent c48dc99
commit 89ce40b
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/VerilogParser.yy b/src/VerilogParser.yy
@@ -155,7 +155,7 @@ port_declaration: port_type_io range.opt identifier {
 internal_ports_declaration: port_type_io range.opt list_of_identifiers {
   constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
   for (auto portIdentifier: $3) {
-    constructor->internalModuleInterfaceCompletePort(Port(portIdentifier, $1, $2));
+    constructor->internalModuleImplementationPort(Port(portIdentifier, $1, $2));
   }
 }