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platgen.log
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Release 14.1 - platgen Xilinx EDK 14.1 Build EDK_P.15xf
(lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc5vlx110tff1136-1 -lang vhdl -intstyle default -lp
lib/ -msg __xps/ise/xmsgprops.lst -parallel yes system.mhs
WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable
is set to '2100@license-srv.eecs.berkeley.edu'.
INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.
INFO:Security:71 - If a license for part 'xc5vlx110t' is available, it will
be possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse /home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs ...
Read MPD definitions ...
Overriding IP level properties ...
Computing clock values...
INFO:EDK:740 - Cannot determine the input clock associated with port :
ilmb_cntlr:BRAM_Clk_A. Clock DRCs will not be performed on this core and
cores connected to it.
INFO:EDK:740 - Cannot determine the input clock associated with port :
dlmb_cntlr:BRAM_Clk_A. Clock DRCs will not be performed on this core and
cores connected to it.
INFO:EDK:1039 - Did not update the value for parameter:
fft_coprocessor_0_to_microblaze_0:C_READ_CLOCK_PERIOD. Top-level frequency
could not be propagated to this IP. Please make sure that you have specified
the frequency of the top-level clock port, and that the clocks are properly
connected.
INFO:EDK:1039 - Did not update the value for parameter:
microblaze_0_to_fft_coprocessor_0:C_READ_CLOCK_PERIOD. Top-level frequency
could not be propagated to this IP. Please make sure that you have specified
the frequency of the top-level clock port, and that the clocks are properly
connected.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0000000000-0x0000ffff) dlmb_cntlr dlmb
(0000000000-0x0000ffff) ilmb_cntlr ilmb
(0x84000000-0x8400ffff) RS232_Uart_1 mb_plb
(0x84400000-0x8440ffff) mdm_0 mb_plb
INFO:EDK:4130 - IPNAME: plb_v46, INSTANCE:mb_plb - tool is overriding PARAMETER
C_PLBV46_NUM_MASTERS value to 2 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_05_a/da
ta/plb_v46_v2_1_0.mpd line 78
INFO:EDK:4130 - IPNAME: plb_v46, INSTANCE:mb_plb - tool is overriding PARAMETER
C_PLBV46_NUM_SLAVES value to 2 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_05_a/da
ta/plb_v46_v2_1_0.mpd line 79
INFO:EDK:4130 - IPNAME: plb_v46, INSTANCE:mb_plb - tool is overriding PARAMETER
C_PLBV46_MID_WIDTH value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_05_a/da
ta/plb_v46_v2_1_0.mpd line 80
INFO:EDK:4130 - IPNAME: plb_v46, INSTANCE:mb_plb - tool is overriding PARAMETER
C_PLBV46_DWIDTH value to 32 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_05_a/da
ta/plb_v46_v2_1_0.mpd line 82
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:ilmb - tool is overriding PARAMETER
C_LMB_NUM_SLAVES value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_b/da
ta/lmb_v10_v2_1_0.mpd line 80
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:dlmb - tool is overriding PARAMETER
C_LMB_NUM_SLAVES value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_b/da
ta/lmb_v10_v2_1_0.mpd line 80
INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:lmb_bram - tool is overriding
PARAMETER C_MEMSIZE value to 0x10000 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a
/data/bram_block_v2_1_0.mpd line 76
INFO:EDK:4130 - IPNAME: xps_uartlite, INSTANCE:RS232_Uart_1 - tool is overriding
PARAMETER C_SPLB_NUM_MASTERS value to 2 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_uartlite_v1_02
_a/data/xps_uartlite_v2_1_0.mpd line 83
INFO:EDK:4130 - IPNAME: mdm, INSTANCE:mdm_0 - tool is overriding PARAMETER
C_SPLB_MID_WIDTH value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: mdm, INSTANCE:mdm_0 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 2 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 93
Checking platform address map ...
Checking platform configuration ...
IPNAME: plb_v46, INSTANCE: mb_plb - 2 master(s) : 2 slave(s)
IPNAME: lmb_v10, INSTANCE: ilmb - 1 master(s) : 1 slave(s)
IPNAME: lmb_v10, INSTANCE: dlmb - 1 master(s) : 1 slave(s)
IPNAME: fsl_v20, INSTANCE: fft_coprocessor_0_to_microblaze_0 - 1 master(s) : 1
slave(s)
IPNAME: fsl_v20, INSTANCE: microblaze_0_to_fft_coprocessor_0 - 1 master(s) : 1
slave(s)
Checking port drivers...
WARNING:EDK:4180 - PORT: bscan_tdo1, CONNECTOR: bscan_tdo1 - No driver found.
Port will be driven to GND -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 239
WARNING:EDK:4180 - PORT: FSL_Rst, CONNECTOR:
microblaze_0_to_fft_coprocessor_0_OPB_Rst - No driver found. Port will be
driven to GND -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/pcores/fft_coprocessor_v1_0
2_a/data/fft_coprocessor_v2_1_0.mpd line 28
WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR:
microblaze_0_to_fft_coprocessor_0_FSL_S_Clk - No driver found. Port will be
driven to GND -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/pcores/fft_coprocessor_v1_0
2_a/data/fft_coprocessor_v2_1_0.mpd line 29
WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR:
fft_coprocessor_0_to_microblaze_0_FSL_M_Clk - No driver found. Port will be
driven to GND -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/pcores/fft_coprocessor_v1_0
2_a/data/fft_coprocessor_v2_1_0.mpd line 34
WARNING:EDK:4181 - PORT: FSL0_S_CLK, CONNECTOR:
fft_coprocessor_0_to_microblaze_0_FSL_S_Clk - floating connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 695
WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR:
microblaze_0_to_fft_coprocessor_0_FSL_M_Clk - floating connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 700
WARNING:EDK:4181 - PORT: bscan_tdi, CONNECTOR: bscan_tdi - floating connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 232
WARNING:EDK:4181 - PORT: bscan_reset, CONNECTOR: bscan_reset - floating
connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 233
WARNING:EDK:4181 - PORT: bscan_shift, CONNECTOR: bscan_shift - floating
connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 234
WARNING:EDK:4181 - PORT: bscan_update, CONNECTOR: bscan_update - floating
connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 235
WARNING:EDK:4181 - PORT: bscan_capture, CONNECTOR: bscan_capture - floating
connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 236
WARNING:EDK:4181 - PORT: bscan_sel1, CONNECTOR: bscan_sel1 - floating connection
-
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 237
WARNING:EDK:4181 - PORT: bscan_drck1, CONNECTOR: bscan_drck1 - floating
connection -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/data/m
dm_v2_1_0.mpd line 238
WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR: sys_periph_reset -
floating connection -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 137
Performing Clock DRCs...
INFO:EDK:4060 - INSTANCE: fft_coprocessor_0_to_microblaze_0, PARAMETER:
C_READ_CLOCK_PERIOD - Did not implement clock DRCs for the parameter.
Top-level frequency could not be propagated to this IP. Please make sure that
you have specified the frequency of the top-level clock port, and that the
clocks are properly connected.
INFO:EDK:4060 - INSTANCE: microblaze_0_to_fft_coprocessor_0, PARAMETER:
C_READ_CLOCK_PERIOD - Did not implement clock DRCs for the parameter.
Top-level frequency could not be propagated to this IP. Please make sure that
you have specified the frequency of the top-level clock port, and that the
clocks are properly connected.
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_D_PLB value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 230
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_I_PLB value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 233
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ADDR_TAG_BITS value to 0 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 334
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_ADDR_TAG value to 0 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 364
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_BRK value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 399
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_NM_BRK value to 1 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_30_a
/data/microblaze_v2_1_0.mpd line 400
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:dlmb_cntlr - tcl is
overriding PARAMETER C_MASK value to 0x04000000 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_
v3_00_b/data/lmb_bram_if_cntlr_v2_1_0.mpd line 87
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:ilmb_cntlr - tcl is
overriding PARAMETER C_MASK value to 0x04000000 -
/opt/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_
v3_00_b/data/lmb_bram_if_cntlr_v2_1_0.mpd line 87
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: The microblaze_0 core has constraints automatically generated by XPS in
implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: The ilmb core has constraints automatically generated by XPS in
implementation/ilmb_wrapper/ilmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: The dlmb core has constraints automatically generated by XPS in
implementation/dlmb_wrapper/dlmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: The fft_coprocessor_0_to_microblaze_0 core has constraints automatically
generated by XPS in
implementation/fft_coprocessor_0_to_microblaze_0_wrapper/fft_coprocessor_0_to_mi
croblaze_0_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: The microblaze_0_to_fft_coprocessor_0 core has constraints automatically
generated by XPS in
implementation/microblaze_0_to_fft_coprocessor_0_wrapper/microblaze_0_to_fft_cop
rocessor_0_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
IPNAME:fft_coprocessor INSTANCE:fft_coprocessor_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 148 - Copying
(BBD-specified) netlist files.
Managing cache ...
IPNAME:plb_v46 INSTANCE:mb_plb -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 40 - Copying
cache implementation netlist
IPNAME:lmb_v10 INSTANCE:ilmb -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 47 - Copying
cache implementation netlist
IPNAME:lmb_v10 INSTANCE:dlmb -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 54 - Copying
cache implementation netlist
IPNAME:lmb_bram_if_cntlr INSTANCE:dlmb_cntlr -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 61 - Copying
cache implementation netlist
IPNAME:lmb_bram_if_cntlr INSTANCE:ilmb_cntlr -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 70 - Copying
cache implementation netlist
IPNAME:bram_block INSTANCE:lmb_bram -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 79 - Copying
cache implementation netlist
IPNAME:xps_uartlite INSTANCE:rs232_uart_1 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 86 - Copying
cache implementation netlist
IPNAME:mdm INSTANCE:mdm_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 115 - Copying
cache implementation netlist
IPNAME:proc_sys_reset INSTANCE:proc_sys_reset_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 127 - Copying
cache implementation netlist
IPNAME:fsl_v20 INSTANCE:fft_coprocessor_0_to_microblaze_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 140 - Copying
cache implementation netlist
Elaborating instances ...
IPNAME:bram_block INSTANCE:lmb_bram -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 79 -
elaborating IP
IPNAME:clock_generator INSTANCE:clock_generator_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 100 -
elaborating IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 0.00 seconds
Constructing platform-level connectivity ...
Completion time: 1.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INFO:EDK:4194 - Running XST parallelly on 2 processors
INSTANCE:microblaze_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 24 - Running
XST synthesis
INSTANCE:clock_generator_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 100 - Running
XST synthesis
INSTANCE:fft_coprocessor_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 148 - Running
XST synthesis
INSTANCE:microblaze_0_to_fft_coprocessor_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 156 - Running
XST synthesis
Running NGCBUILD ...
IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 24 - Running
NGCBUILD
IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 100 - Running
NGCBUILD
IPNAME:system_fft_coprocessor_0_wrapper INSTANCE:fft_coprocessor_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 148 - Running
NGCBUILD
IPNAME:system_microblaze_0_to_fft_coprocessor_0_wrapper
INSTANCE:microblaze_0_to_fft_coprocessor_0 -
/home/cc/cs150/sp13/class/cs150-ac/microblaze_fft/system.mhs line 156 - Running
NGCBUILD
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
Total run time: 898.00 seconds