spi timing fixes

components/driver/spi_master.c

@@ -415,7 +415,7 @@ static void spi_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) {
         int bestpre=-1;
         int besterr=0;
         int errval;
-        for (n=1; n<=64; n++) {
+        for (n=2; n<=64; n++) {
             //Effectively, this does pre=round((fapb/n)/hz).
             pre=((fapb/n)+(hz/2))/hz;
             if (pre<=0) pre=1;
@@ -431,8 +431,8 @@ static void spi_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) {
         n=bestn;
         pre=bestpre;
         l=n;
-        //This effectively does round((duty_cycle*n)/256)
-        h=(duty_cycle*n+127)/256;
+        //This effectively does floor((duty_cycle*n)/256)
+        h=(n*duty_cycle)/256;
         if (h<=0) h=1;
 
         hw->clock.clk_equ_sysclk=0;
@@ -523,7 +523,7 @@ static void IRAM_ATTR spi_intr(void *arg)
 
             //Configure polarity
             //SPI iface needs to be configured for a delay unless it is not routed through GPIO and clock is >=apb/2
-            int nodelay=(host->no_gpio_matrix && dev->cfg.clock_speed_hz >= (apbclk/2));
+            int nodelay=((host->no_gpio_matrix && dev->cfg.clock_speed_hz >= (apbclk/2)) || (!host->no_gpio_matrix && dev->cfg.clock_speed_hz >= (apbclk/4)));
             if (dev->cfg.mode==0) {
                 host->hw->pin.ck_idle_edge=0;
                 host->hw->user.ck_out_edge=0;