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Merge branch '2023-03-29-assorted-platform-updates' into next
- Assorted TI, Apple M1, and mpc83xx improvements / cleanups.
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27 changes: 27 additions & 0 deletions
27
arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,27 @@ | ||
| // SPDX-License-Identifier: GPL-2.0 | ||
| /* | ||
| * IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0 | ||
| * Copyright (c) Siemens AG, 2022 | ||
| * | ||
| * Authors: | ||
| * Chao Zeng <chao.zeng@siemens.com> | ||
| * Jan Kiszka <jan.kiszka@siemens.com> | ||
| */ | ||
|
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||
| /dts-v1/; | ||
| /plugin/; | ||
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| #include <dt-bindings/phy/phy.h> | ||
| #include <dt-bindings/gpio/gpio.h> | ||
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| &pcie0_rc { | ||
| num-lanes = <1>; | ||
| phys = <&serdes0 PHY_TYPE_PCIE 1>; | ||
| phy-names = "pcie-phy0"; | ||
| reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; | ||
| status = "okay"; | ||
| }; | ||
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| &pcie1_rc { | ||
| status = "okay"; | ||
| }; |
47 changes: 47 additions & 0 deletions
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arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,47 @@ | ||
| // SPDX-License-Identifier: GPL-2.0 | ||
| /* | ||
| * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0 | ||
| * Copyright (c) Siemens AG, 2022 | ||
| * | ||
| * Authors: | ||
| * Chao Zeng <chao.zeng@siemens.com> | ||
| * Jan Kiszka <jan.kiszka@siemens.com> | ||
| */ | ||
|
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| /dts-v1/; | ||
| /plugin/; | ||
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| #include <dt-bindings/phy/phy.h> | ||
| #include <dt-bindings/gpio/gpio.h> | ||
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| &serdes0 { | ||
| assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; | ||
| }; | ||
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| &pcie0_rc { | ||
| status = "disabled"; | ||
| }; | ||
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| &pcie1_rc { | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&minipcie_pins_default>; | ||
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| num-lanes = <1>; | ||
| phys = <&serdes1 PHY_TYPE_PCIE 0>; | ||
| phy-names = "pcie-phy0"; | ||
| reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; | ||
| status = "okay"; | ||
| }; | ||
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| &dwc3_0 { | ||
| assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ | ||
| <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ | ||
| phys = <&serdes0 PHY_TYPE_USB3 0>; | ||
| phy-names = "usb3-phy"; | ||
| }; | ||
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| &usb0 { | ||
| maximum-speed = "super-speed"; | ||
| snps,dis-u1-entry-quirk; | ||
| snps,dis-u2-entry-quirk; | ||
| }; |
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