RTL code of some arbitration algorithms which are able to synthesize. I tried to synthesize on Quartus II, a software of Altera for FPGA.
RTL list
- Absolute Fixed Priority Arbiter
ArbFixedPriorityAbs.v
- Non-Absolute Fixed Priority Arbiter
ArbFixedPriorityNAbs.v
- Non-Absolute Fixed Priority Arbiter with LOCK function
ArbFixedPriorityLocked.v
- Dynamic priority arbiter
ArbDynamicPriority.v
- Simple Round Robin with a counter
ArbSimpleRR.v
- Round Robin arbiter with Priority logic
ArbPriorityRR.v
- Balance Round Robin
ArbBalanceRR.v
Detail Description
http://nguyenquanicd.blogspot.com/search/label/Arbiter?&max-results=5
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