GitHub - nhandyal/Verilog-Spectrum-Analyzer: FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.

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FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
iseconfig		iseconfig
BlockRamSin.v		BlockRamSin.v
BlockRamSin_summary.html		BlockRamSin_summary.html
COS_LUT.lso		COS_LUT.lso
COS_LUT.v		COS_LUT.v
COS_LUT_summary.html		COS_LUT_summary.html
COS_LUT_tb.udo		COS_LUT_tb.udo
COS_LUT_tb.v		COS_LUT_tb.v
COS_LUT_tb_wave.fdo		COS_LUT_tb_wave.fdo
FFT_SM.v		FFT_SM.v
FFT_alg.v		FFT_alg.v
FFT_state1.lso		FFT_state1.lso
FFT_state1.v		FFT_state1.v
RAM_tb.udo		RAM_tb.udo
RAM_tb.v		RAM_tb.v
RAM_tb_wave.fdo		RAM_tb_wave.fdo
SIN_LUT.bmm		SIN_LUT.bmm
SIN_LUT.lso		SIN_LUT.lso
SIN_LUT.v		SIN_LUT.v
SIN_LUT_summary.html		SIN_LUT_summary.html
SIN_LUT_tb.udo		SIN_LUT_tb.udo
SIN_LUT_tb.v		SIN_LUT_tb.v
SIN_LUT_tb_wave.fdo		SIN_LUT_tb_wave.fdo
Spectrum_Analyzer.gise		Spectrum_Analyzer.gise
Spectrum_Analyzer.xise		Spectrum_Analyzer.xise
bitRevOrder.cmd_log		bitRevOrder.cmd_log
bitRevOrder.lso		bitRevOrder.lso
bitRevOrder.sym		bitRevOrder.sym
bitRevOrderSM.cmd_log		bitRevOrderSM.cmd_log
bitRevOrderSM.lso		bitRevOrderSM.lso
bitRevOrderSM.sym		bitRevOrderSM.sym
bitRevOrderSM.v		bitRevOrderSM.v
bitRevOrderTest.jhd		bitRevOrderTest.jhd
bitRevOrderTest.sch		bitRevOrderTest.sch
bitRevOrderTest_bitRevOrderTest_sch_tb.udo		bitRevOrderTest_bitRevOrderTest_sch_tb.udo
bitRevOrderTest_bitRevOrderTest_sch_tb_wave.fdo		bitRevOrderTest_bitRevOrderTest_sch_tb_wave.fdo
bitRevOrderTest_tb.v		bitRevOrderTest_tb.v
bitRevOrder_SM_Top.jhd		bitRevOrder_SM_Top.jhd
bitRevOrder_SM_Top.sch		bitRevOrder_SM_Top.sch
bitRevOrder_SM_Top.schbak		bitRevOrder_SM_Top.schbak
bitRevOrder_SM_Top.schcmd		bitRevOrder_SM_Top.schcmd
bitRevOrder_SM_Top_bitRevOrder_SM_Top_sch_tb.udo		bitRevOrder_SM_Top_bitRevOrder_SM_Top_sch_tb.udo
bitRevOrder_SM_Top_bitRevOrder_SM_Top_sch_tb_wave.fdo		bitRevOrder_SM_Top_bitRevOrder_SM_Top_sch_tb_wave.fdo
bitRevOrder_SM_Top_tb.v		bitRevOrder_SM_Top_tb.v
bitRevOrder_tb.udo		bitRevOrder_tb.udo
bitRevOrder_tb.v		bitRevOrder_tb.v
bitRevOrder_tb_wave.fdo		bitRevOrder_tb_wave.fdo
bitRevRam.cmd_log		bitRevRam.cmd_log
bitRevRam.sym		bitRevRam.sym
bitRevRam.udo		bitRevRam.udo
bitRevRam.v		bitRevRam.v
bitRevRam_tb.udo		bitRevRam_tb.udo
bitRevRam_tb.v		bitRevRam_tb.v
bitRevRam_tb_wave.fdo		bitRevRam_tb_wave.fdo
bitRevRam_wave.fdo		bitRevRam_wave.fdo
bitrevorder_test_top.v		bitrevorder_test_top.v
bitrevorder_test_top2.jhd		bitrevorder_test_top2.jhd
bitrevorder_test_top2.sch		bitrevorder_test_top2.sch
bitrevorder_test_top2_bitrevorder_test_top2_sch_tb.udo		bitrevorder_test_top2_bitrevorder_test_top2_sch_tb.udo
bitrevorder_test_top2_bitrevorder_test_top2_sch_tb_wave.fdo		bitrevorder_test_top2_bitrevorder_test_top2_sch_tb_wave.fdo
bitrevorder_test_top2_tb.v		bitrevorder_test_top2_tb.v
bitrevorder_test_top2_tb.v.bak		bitrevorder_test_top2_tb.v.bak
complexMult.v		complexMult.v
complexMultN.v		complexMultN.v
complexMult_BottomBranch_Twiddle.bmm		complexMult_BottomBranch_Twiddle.bmm
complexMult_BottomBranch_Twiddle.lso		complexMult_BottomBranch_Twiddle.lso
counter9bit.lso		counter9bit.lso
counter9bit.v		counter9bit.v
counter9bit_tb.udo		counter9bit_tb.udo
counter9bit_tb.v		counter9bit_tb.v
counter9bit_tb.v.bak		counter9bit_tb.v.bak
counter9bit_tb_wave.fdo		counter9bit_tb_wave.fdo
ee201l_spectrum_analyzer_UCF.ucf		ee201l_spectrum_analyzer_UCF.ucf
inputData_IRAM.v		inputData_IRAM.v
inputData_RRAM.lso		inputData_RRAM.lso
inputData_RRAM.v		inputData_RRAM.v
inputData_RRAM_tb.udo		inputData_RRAM_tb.udo
inputData_RRAM_tb.v		inputData_RRAM_tb.v
inputData_RRAM_tb.v.bak		inputData_RRAM_tb.v.bak
inputData_RRAM_tb_wave.fdo		inputData_RRAM_tb_wave.fdo
inputData_RRAM_test.cmd_log		inputData_RRAM_test.cmd_log
inputData_RRAM_test.lso		inputData_RRAM_test.lso
inputData_RRAM_test.sym		inputData_RRAM_test.sym
inputData_RRAMv2.lso		inputData_RRAMv2.lso
inputData_RRAMv2.v		inputData_RRAMv2.v
ram_test.v		ram_test.v
sch2HdlBatchFile		sch2HdlBatchFile
test.jhd		test.jhd
test.lso		test.lso
test.sch		test.sch
test.schlog		test.schlog
test_tb.udo		test_tb.udo
test_tb.v		test_tb.v
test_tb_wave.fdo		test_tb_wave.fdo
test_test_sch_tb.udo		test_test_sch_tb.udo
test_test_sch_tb_wave.fdo		test_test_sch_tb_wave.fdo
transcript		transcript
wave.do		wave.do
waveBitRevOrderTop		waveBitRevOrderTop
waveCOSLUT.do		waveCOSLUT.do

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FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.

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