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Release 24.0 (2024 Q1)

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@mraj8370-NI mraj8370-NI released this 31 Jan 10:26
· 1 commit to main since this release
v24.0
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New Features

  • Removed the restriction to keep port 50505 free. Users can configure the tool to use any free port by creating a JSON file at C:\Program Files\National Instruments\IP to FPGA Conversion Utility\ip2fpgaCLIConfig.json.
    Example:
{
  "ServerPort": 50507
}
  • Added the ability to integrate additional NI FPGA hardware into the NI FPGA bitfile generation workflow. Contact https://www.ni.com/support for more info.

Bug Fixes

Bug Number Description
2558945 HDL Coder toolbox version 23.5 does not work with MATLAB 2023b.
2488773 Bitfile generated for Target PXIe-7891 is not compatible with PXIe-7891 Hardware.

Known Issues

Bug Number Description
2295676 Opening HDL workflow advisor for a model with NI FPGA Bitfile Generation workflow throws an "Unable to load from the restore point." error.
Workaround: Replace "utilHandle_HDLAdvisorData.p" in "C:\Program Files\MATLAB\<MATLAB_version>\toolbox\hdlcoder\hdlcoder\hdlwa\private\" with the file provided in this release asset and restart MATLAB.
Note: Issue observed from MATLAB 2022b Update 4 to MATLAB 2023a Update 2, Fixed in MATLAB 2023a Update 3
2330587 Running/Importing scripts that are created using HDL Coder Support Package for NI hardware 23.0 and below throws "Unrecognized property 'DesiredDerivedFrequency' for class 'HWCli.NIWorkflowConfig'"
Workaround: Remove 'hWC.DesiredDerivedFrequency' from the script.
2177807 LabVIEW security window pops up for the first run of NI FPGA Bitfile Generation workflow with LabVIEW 2021
Note: Add ServerRunner_CLI.vi in the permissions list and try again.
2177772 Upgrading HDL Coder Support Package for NI hardware may result in unexpected behavior
Workaround: Clear/Delete slprj folder before running MATLAB.
2464137 Using HDL Coder Support Package for NI FPGA Hardware with Non English Language OS produces error
Workaround: Change the Region settings to English.
2590831 Compile Project task sometimes results in an Encrypted Envelope error.
Workaround: This is typically due to syntax errors in the generated VHDL. These errors get masked due to encryption. Compile the model using the "Generic ASIC/FPGA" workflow to find the underlying syntax error.

Known Limitations

  • Only supports VHDL.
  • No support for double precision ports (single precision is supported).
  • Only registers CPU-FPGA communication through Read/Write controls.
  • No support for purely combinatorial circuits, such as circuits without clocks.
  • Cannot connect array and complex ports to board I/O.
  • Post code generation ports in VHDL entity that do not have a corresponding model port(e.g., clk_enable) will be mapped to registers.
  • Save and Load Restore Point does not work.
  • Auto-restore last exited session does not work.
  • Only English LabVIEW is supported.
Assets 3