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Add acyclic frame functionality #54
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Tx Acyclic Write to Hardware
- Is this property node access for the triggerable frames going to hit the massive performance problem we found in the Ballard custom device? Should we just use an in place unbundle since we're in the same class?
- Potential same question as above for Transmitted Messages in the scheduled
Write to Hardware
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Bleep bloop! LabVIEW Diff Robot here with some diffs served up hot for your pull request. Notice something funny? Help fix me on my GitHub repo. AIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Execution Unit Factory.lvclass--Create Execution Unit.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Execution Unit.lvclass--Get VS Channel Handles and Messages.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Execution Unit.lvclass--Read Module Reference.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Shared Resources Factory.lvclass--Get 1553 Configuration.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Shared Resources.lvclass--Read Bus Controller Message Configurations.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Tx Acyclic Execution Unit.lvclass--Initialize.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Tx Acyclic Execution Unit.lvclass--Populate Triggerable Frames with Messages.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Tx Acyclic Execution Unit.lvclass--Read Triggerable Frames.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Tx Acyclic Execution Unit.lvclass--Tx Acyclic Construct.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Tx Acyclic Execution Unit.lvclass--Write to Hardware.vi.pngAIM MIL-STD-1553 Engine.lvlib--Implementation.lvlib--Tx Execution Unit.lvclass--Write to Hardware.vi.png |
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Is the skipping of driver calls when transfer IDs aren't found just something we need to do or is there something we need to report back to the user to tell them that something is incorrectly configured?
We should probably put an error in the log file and improve our frame parsing to not persist empty frames/messages into the compiled data. |
We can do what @Karl-G1 recommended as well, but we also need the case structures because if there is ever an empty array in any of those cases, Veristand crashes. EDIT: I added an issue (see link below) for this to be addressed in the future. |
What does this Pull Request accomplish?
Adds Acyclic frame transmission to the engine in the Tx Acyclic Execution Unit (in a future PR, should rename Tx Acyclic EU to Trigger EU)
Why should this Pull Request be merged?
What testing has been done?
Automated tests have been run, and manually tested the acyclic frames. Tried running with an empty frame of each type, and no crash occurred.