forked from steveicarus/iverilog
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pform.cc
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pform.cc
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/*
* Copyright (c) 1998-2007 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: pform.cc,v 1.148 2007/06/12 04:05:45 steve Exp $"
#endif
# include "config.h"
# include "compiler.h"
# include "pform.h"
# include "parse_misc.h"
# include "parse_api.h"
# include "PEvent.h"
# include "PUdp.h"
# include "PGenerate.h"
# include "PSpec.h"
# include <list>
# include <map>
# include <assert.h>
# include <stack>
# include <typeinfo>
# include <sstream>
map<perm_string,Module*> pform_modules;
map<perm_string,PUdp*> pform_primitives;
/*
* The lexor accesses the vl_* variables.
*/
string vl_file = "";
extern int VLparse();
/* This tracks the current module being processed. There can only be
exactly one module currently being parsed, since verilog does not
allow nested module definitions. */
static Module*pform_cur_module = 0;
bool pform_library_flag = false;
/* increment this for generate schemes within a module, and set it
to zero when a new module starts. */
static unsigned scope_generate_counter = 1;
/* This tracks the current generate scheme being processed. This is
always within a module. */
static PGenerate*pform_cur_generate = 0;
static NetNet::Type pform_default_nettype = NetNet::WIRE;
/*
* These variables track the current time scale, as well as where the
* timescale was set. This supports warnings about tangled timescales.
*/
static int pform_time_unit = 0;
static int pform_time_prec = 0;
static char*pform_timescale_file = 0;
static unsigned pform_timescale_line = 0;
/*
* The scope stack and the following functions handle the processing
* of scope. As I enter a scope, the push function is called, and as I
* leave a scope the pop function is called. Entering tasks, functions
* and named blocks causes scope to be pushed and popped. The module
* name is not included in this scope stack.
*
* The hier_name function, therefore, converts the name to the scoped
* name within the module currently in progress. It never includes an
* instance name.
*
* The scope stack does not include any scope created by a generate
* scheme.
*/
static pform_name_t scope_stack;
void pform_push_scope(char*name)
{
scope_stack.push_back(name_component_t(lex_strings.make(name)));
}
void pform_pop_scope()
{
scope_stack.pop_back();
}
static pform_name_t hier_name(const char*tail)
{
pform_name_t name = scope_stack;
name.push_back(name_component_t(lex_strings.make(tail)));
return name;
}
static PWire*get_wire_in_module(const pform_name_t&name)
{
/* Note that if we are processing a generate, then the
scope depth will be empty because generate schemes
cannot be within sub-scopes. Only directly in
modules. */
if (pform_cur_generate)
return pform_cur_generate->get_wire(name);
return pform_cur_module->get_wire(name);
}
void pform_set_default_nettype(NetNet::Type type,
const char*file, unsigned lineno)
{
pform_default_nettype = type;
if (pform_cur_module) {
cerr << file<<":"<<lineno << ": error: "
<< "`default_nettype directives must appear" << endl;
cerr << file<<":"<<lineno << ": : "
<< "outside module definitions. The containing" << endl;
cerr << file<<":"<<lineno << ": : "
<< "module " << pform_cur_module->mod_name()
<< " starts on line "
<< pform_cur_module->get_line() << "." << endl;
error_count += 1;
}
}
/*
* The lexor calls this function to set the active timescale when it
* detects a `timescale directive. The function saves the directive
* values (for use by modules) and if warnings are enabled checks to
* see if some modules have no timescale.
*/
void pform_set_timescale(int unit, int prec,
const char*file, unsigned lineno)
{
bool first_flag = true;
assert(unit >= prec);
pform_time_unit = unit;
pform_time_prec = prec;
if (pform_timescale_file) {
free(pform_timescale_file);
first_flag = false;
}
pform_timescale_file = strdup(file);
pform_timescale_line = lineno;
if (warn_timescale && first_flag && (pform_modules.size() > 0)) {
cerr << file << ":" << lineno << ": warning: "
<< "Some modules have no timescale. This may cause"
<< endl;
cerr << file << ":" << lineno << ": : "
<< "confusing timing results. Affected modules are:"
<< endl;
map<perm_string,Module*>::iterator mod;
for (mod = pform_modules.begin()
; mod != pform_modules.end() ; mod++) {
const Module*mp = (*mod).second;
cerr << file << ":" << lineno << ": : "
<< " -- module " << (*mod).first
<< " declared here: " << mp->get_line() << endl;
}
}
}
verinum* pform_verinum_with_size(verinum*siz, verinum*val,
const char*file, unsigned lineno)
{
assert(siz->is_defined());
unsigned long size = siz->as_ulong();
verinum::V pad;
switch (val->get(val->len()-1)) {
case verinum::Vz:
pad = verinum::Vz;
break;
case verinum::Vx:
pad = verinum::Vx;
break;
default:
pad = verinum::V0;
break;
}
verinum*res = new verinum(pad, size, true);
unsigned copy = val->len();
if (res->len() < copy)
copy = res->len();
for (unsigned idx = 0 ; idx < copy ; idx += 1) {
res->set(idx, val->get(idx));
}
res->has_sign(val->has_sign());
bool trunc_flag = false;
for (unsigned idx = copy ; idx < val->len() ; idx += 1) {
if (val->get(idx) != pad) {
trunc_flag = true;
break;
}
}
if (trunc_flag) {
cerr << file << ":" << lineno << ": warning: Numeric constant "
<< "truncated to " << copy << " bits." << endl;
}
delete siz;
delete val;
return res;
}
void pform_startmodule(const char*name, const char*file, unsigned lineno,
svector<named_pexpr_t*>*attr)
{
assert( pform_cur_module == 0 );
perm_string lex_name = lex_strings.make(name);
pform_cur_module = new Module(lex_name);
pform_cur_module->time_unit = pform_time_unit;
pform_cur_module->time_precision = pform_time_prec;
pform_cur_module->default_nettype = pform_default_nettype;
pform_cur_module->set_file(file);
pform_cur_module->set_lineno(lineno);
pform_cur_module->library_flag = pform_library_flag;
/* The generate scheme numbering starts with *1*, not
zero. That's just the way it is, thanks to the standard. */
scope_generate_counter = 1;
if (warn_timescale && pform_timescale_file
&& (strcmp(pform_timescale_file,file) != 0)) {
cerr << pform_cur_module->get_line() << ": warning: "
<< "timescale for " << name
<< " inherited from another file." << endl;
cerr << pform_timescale_file << ":" << pform_timescale_line
<< ": ...: The inherited timescale is here." << endl;
}
if (attr) {
for (unsigned idx = 0 ; idx < attr->count() ; idx += 1) {
named_pexpr_t*tmp = (*attr)[idx];
pform_cur_module->attributes[tmp->name] = tmp->parm;
}
}
}
/*
* This function is called by the parser to make a simple port
* reference. This is a name without a .X(...), so the internal name
* should be generated to be the same as the X.
*/
Module::port_t* pform_module_port_reference(char*name,
const char*file,
unsigned lineno)
{
Module::port_t*ptmp = new Module::port_t;
PEIdent*tmp = new PEIdent(lex_strings.make(name));
tmp->set_file(file);
tmp->set_lineno(lineno);
ptmp->name = lex_strings.make(name);
ptmp->expr = svector<PEIdent*>(1);
ptmp->expr[0] = tmp;
return ptmp;
}
void pform_module_set_ports(svector<Module::port_t*>*ports)
{
assert(pform_cur_module);
/* The parser parses ``module foo()'' as having one
unconnected port, but it is really a module with no
ports. Fix it up here. */
if (ports && (ports->count() == 1) && ((*ports)[0] == 0)) {
delete ports;
ports = 0;
}
if (ports != 0) {
pform_cur_module->ports = *ports;
delete ports;
}
}
void pform_endmodule(const char*name)
{
assert(pform_cur_module);
perm_string mod_name = pform_cur_module->mod_name();
assert(strcmp(name, mod_name) == 0);
map<perm_string,Module*>::const_iterator test =
pform_modules.find(mod_name);
if (test != pform_modules.end()) {
ostringstream msg;
msg << "Module " << name << " was already declared here: "
<< (*test).second->get_line() << endl;
VLerror(msg.str().c_str());
pform_cur_module = 0;
return;
}
pform_modules[mod_name] = pform_cur_module;
pform_cur_module = 0;
}
void pform_genvars(list<perm_string>*names)
{
list<perm_string>::const_iterator cur;
for (cur = names->begin(); cur != names->end() ; *cur++) {
pform_cur_module->genvars.push_back( *cur );
}
delete names;
}
void pform_start_generate_for(const struct vlltype&li,
char*ident1, PExpr*init,
PExpr*test,
char*ident2, PExpr*next)
{
PGenerate*gen = new PGenerate(scope_generate_counter++);
gen->set_file(li.text);
gen->set_lineno(li.first_line);
// For now, assume that generates do not nest.
gen->parent = pform_cur_generate;
pform_cur_generate = gen;
pform_cur_generate->scheme_type = PGenerate::GS_LOOP;
pform_cur_generate->loop_index = lex_strings.make(ident1);
pform_cur_generate->loop_init = init;
pform_cur_generate->loop_test = test;
pform_cur_generate->loop_step = next;
delete[]ident1;
delete[]ident2;
}
void pform_generate_block_name(char*name)
{
assert(pform_cur_generate != 0);
assert(pform_cur_generate->scope_name == 0);
pform_cur_generate->scope_name = lex_strings.make(name);
delete[]name;
}
void pform_endgenerate()
{
assert(pform_cur_generate != 0);
assert(pform_cur_module);
PGenerate*cur = pform_cur_generate;
pform_cur_generate = cur->parent;
if (pform_cur_generate != 0)
pform_cur_generate->generates.push_back(cur);
else
pform_cur_module->generate_schemes.push_back(cur);
}
bool pform_expression_is_constant(const PExpr*ex)
{
return ex->is_constant(pform_cur_module);
}
MIN_TYP_MAX min_typ_max_flag = TYP;
unsigned min_typ_max_warn = 10;
PExpr* pform_select_mtm_expr(PExpr*min, PExpr*typ, PExpr*max)
{
PExpr*res = 0;
switch (min_typ_max_flag) {
case MIN:
res = min;
delete typ;
delete max;
break;
case TYP:
res = typ;
delete min;
delete max;
break;
case MAX:
res = max;
delete min;
delete typ;
break;
}
if (min_typ_max_warn > 0) {
cerr << res->get_line() << ": warning: choosing ";
switch (min_typ_max_flag) {
case MIN:
cerr << "min";
break;
case TYP:
cerr << "typ";
break;
case MAX:
cerr << "max";
break;
}
cerr << " expression." << endl;
min_typ_max_warn -= 1;
}
return res;
}
static void process_udp_table(PUdp*udp, list<string>*table,
const char*file, unsigned lineno)
{
const bool synchronous_flag = udp->sequential;
/* Interpret and check the table entry strings, to make sure
they correspond to the inputs, output and output type. Make
up vectors for the fully interpreted result that can be
placed in the PUdp object.
The table strings are made up by the parser to be two or
three substrings seperated by ';', i.e.:
0101:1:1 (synchronous device entry)
0101:0 (combinational device entry)
The parser doesn't check that we got the right kind here,
so this loop must watch out. */
svector<string> input (table->size());
svector<char> current (table->size());
svector<char> output (table->size());
{ unsigned idx = 0;
for (list<string>::iterator cur = table->begin()
; cur != table->end()
; cur ++, idx += 1) {
string tmp = *cur;
/* Pull the input values from the string. */
assert(tmp.find(':') == (udp->ports.count() - 1));
input[idx] = tmp.substr(0, udp->ports.count()-1);
tmp = tmp.substr(udp->ports.count()-1);
assert(tmp[0] == ':');
/* If this is a synchronous device, get the current
output string. */
if (synchronous_flag) {
if (tmp.size() != 4) {
cerr << file<<":"<<lineno << ": error: "
<< "Invalid table format for"
<< " sequential primitive." << endl;
error_count += 1;
break;
}
assert(tmp.size() == 4);
current[idx] = tmp[1];
tmp = tmp.substr(2);
} else if (tmp.size() != 2) {
cerr << file<<":"<<lineno << ": error: "
<< "Invalid table format for"
<< " combinational primitive." << endl;
error_count += 1;
break;
}
/* Finally, extract the desired output. */
assert(tmp.size() == 2);
output[idx] = tmp[1];
}
}
udp->tinput = input;
udp->tcurrent = current;
udp->toutput = output;
}
void pform_make_udp(perm_string name, list<string>*parms,
svector<PWire*>*decl, list<string>*table,
Statement*init_expr,
const char*file, unsigned lineno)
{
unsigned local_errors = 0;
assert(parms->size() > 0);
/* Put the declarations into a map, so that I can check them
off with the parameters in the list. If the port is already
in the map, merge the port type. I will rebuild a list
of parameters for the PUdp object. */
map<string,PWire*> defs;
for (unsigned idx = 0 ; idx < decl->count() ; idx += 1) {
pform_name_t pname = (*decl)[idx]->path();
string port_name = peek_tail_name(pname).str();
if (PWire*cur = defs[port_name]) {
bool rc = true;
assert((*decl)[idx]);
if ((*decl)[idx]->get_port_type() != NetNet::PIMPLICIT) {
rc = cur->set_port_type((*decl)[idx]->get_port_type());
assert(rc);
}
if ((*decl)[idx]->get_wire_type() != NetNet::IMPLICIT) {
rc = cur->set_wire_type((*decl)[idx]->get_wire_type());
assert(rc);
}
} else {
defs[port_name] = (*decl)[idx];
}
}
/* Put the parameters into a vector of wire descriptions. Look
in the map for the definitions of the name. In this loop,
the parms list in the list of ports in the port list of the
UDP declaration, and the defs map maps that name to a
PWire* created by an input or output declaration. */
svector<PWire*> pins (parms->size());
svector<string> pin_names (parms->size());
{ list<string>::iterator cur;
unsigned idx;
for (cur = parms->begin(), idx = 0
; cur != parms->end()
; idx++, cur++) {
pins[idx] = defs[*cur];
pin_names[idx] = *cur;
}
}
/* Check that the output is an output and the inputs are
inputs. I can also make sure that only the single output is
declared a register, if anything. The possible errors are:
-- an input port (not the first) is missing an input
declaration.
-- An input port is declared output.
*/
assert(pins.count() > 0);
do {
if (pins[0] == 0) {
cerr << file<<":"<<lineno << ": error: "
<< "Output port of primitive " << name
<< " missing output declaration." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Try: output " << pin_names[0] << ";"
<< endl;
error_count += 1;
local_errors += 1;
break;
}
if (pins[0]->get_port_type() != NetNet::POUTPUT) {
cerr << file<<":"<<lineno << ": error: "
<< "The first port of a primitive"
<< " must be an output." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Try: output " << pin_names[0] << ";"
<< endl;
error_count += 1;
local_errors += 1;
break;;
}
} while (0);
for (unsigned idx = 1 ; idx < pins.count() ; idx += 1) {
if (pins[idx] == 0) {
cerr << file<<":"<<lineno << ": error: "
<< "Port " << (idx+1)
<< " of primitive " << name << " missing"
<< " input declaration." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Try: input " << pin_names[idx] << ";"
<< endl;
error_count += 1;
local_errors += 1;
continue;
}
if (pins[idx]->get_port_type() != NetNet::PINPUT) {
cerr << file<<":"<<lineno << ": error: "
<< "Input port " << (idx+1)
<< " of primitive " << name
<< " has an output (or missing) declaration." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Note that only the first port can be an output."
<< endl;
cerr << file<<":"<<lineno << ": : "
<< "Try \"input " << name << ";\""
<< endl;
error_count += 1;
local_errors += 1;
continue;
}
if (pins[idx]->get_wire_type() == NetNet::REG) {
cerr << file<<":"<<lineno << ": error: "
<< "Port " << (idx+1)
<< " of primitive " << name << " is an input port"
<< " with a reg declaration." << endl;
cerr << file<<":"<<lineno << ": : "
<< "primitive inputs cannot be reg."
<< endl;
error_count += 1;
local_errors += 1;
continue;
}
}
if (local_errors > 0) {
delete parms;
delete decl;
delete table;
delete init_expr;
return;
}
/* Verify the "initial" statement, if present, to be sure that
it only assigns to the output and the output is
registered. Then save the initial value that I get. */
verinum::V init = verinum::Vx;
if (init_expr) {
// XXXX
assert(pins[0]->get_wire_type() == NetNet::REG);
PAssign*pa = dynamic_cast<PAssign*>(init_expr);
assert(pa);
const PEIdent*id = dynamic_cast<const PEIdent*>(pa->lval());
assert(id);
// XXXX
//assert(id->name() == pins[0]->name());
const PENumber*np = dynamic_cast<const PENumber*>(pa->rval());
assert(np);
init = np->value()[0];
}
// Put the primitive into the primitives table
if (pform_primitives[name]) {
VLerror("UDP primitive already exists.");
} else {
PUdp*udp = new PUdp(name, parms->size());
// Detect sequential udp.
if (pins[0]->get_wire_type() == NetNet::REG)
udp->sequential = true;
// Make the port list for the UDP
for (unsigned idx = 0 ; idx < pins.count() ; idx += 1)
udp->ports[idx] = peek_tail_name(pins[idx]->path());
process_udp_table(udp, table, file, lineno);
udp->initial = init;
pform_primitives[name] = udp;
}
/* Delete the excess tables and lists from the parser. */
delete parms;
delete decl;
delete table;
delete init_expr;
}
void pform_make_udp(perm_string name, bool synchronous_flag,
perm_string out_name, PExpr*init_expr,
list<perm_string>*parms, list<string>*table,
const char*file, unsigned lineno)
{
svector<PWire*> pins(parms->size() + 1);
/* Make the PWire for the output port. */
pins[0] = new PWire(hier_name(out_name),
synchronous_flag? NetNet::REG : NetNet::WIRE,
NetNet::POUTPUT,
IVL_VT_LOGIC);
pins[0]->set_file(file);
pins[0]->set_lineno(lineno);
/* Make the PWire objects for the input ports. */
{ list<perm_string>::iterator cur;
unsigned idx;
for (cur = parms->begin(), idx = 1
; cur != parms->end()
; idx += 1, cur++) {
assert(idx < pins.count());
pins[idx] = new PWire(hier_name(*cur),
NetNet::WIRE,
NetNet::PINPUT,
IVL_VT_LOGIC);
pins[idx]->set_file(file);
pins[idx]->set_lineno(lineno);
}
assert(idx == pins.count());
}
/* Verify the initial expression, if present, to be sure that
it only assigns to the output and the output is
registered. Then save the initial value that I get. */
verinum::V init = verinum::Vx;
if (init_expr) {
// XXXX
assert(pins[0]->get_wire_type() == NetNet::REG);
PAssign*pa = dynamic_cast<PAssign*>(init_expr);
assert(pa);
const PEIdent*id = dynamic_cast<const PEIdent*>(pa->lval());
assert(id);
// XXXX
//assert(id->name() == pins[0]->name());
const PENumber*np = dynamic_cast<const PENumber*>(pa->rval());
assert(np);
init = np->value()[0];
}
// Put the primitive into the primitives table
if (pform_primitives[name]) {
VLerror("UDP primitive already exists.");
} else {
PUdp*udp = new PUdp(name, pins.count());
// Detect sequential udp.
udp->sequential = synchronous_flag;
// Make the port list for the UDP
for (unsigned idx = 0 ; idx < pins.count() ; idx += 1)
udp->ports[idx] = peek_tail_name(pins[idx]->path());
assert(udp);
assert(table);
process_udp_table(udp, table, file, lineno);
udp->initial = init;
pform_primitives[name] = udp;
}
delete parms;
delete table;
delete init_expr;
}
/*
* This function attaches a range to a given name. The function is
* only called by the parser within the scope of the net declaration,
* and the name that I receive only has the tail component.
*/
static void pform_set_net_range(const char* name,
const svector<PExpr*>*range,
bool signed_flag,
ivl_variable_type_t dt)
{
PWire*cur = get_wire_in_module(hier_name(name));
if (cur == 0) {
VLerror("error: name is not a valid net.");
return;
}
if (range == 0) {
/* This is the special case that we really mean a
scalar. Set a fake range. */
cur->set_range(0, 0);
} else {
assert(range->count() == 2);
assert((*range)[0]);
assert((*range)[1]);
cur->set_range((*range)[0], (*range)[1]);
}
cur->set_signed(signed_flag);
if (dt != IVL_VT_NO_TYPE)
cur->set_data_type(dt);
}
void pform_set_net_range(list<perm_string>*names,
svector<PExpr*>*range,
bool signed_flag,
ivl_variable_type_t dt)
{
assert((range == 0) || (range->count() == 2));
for (list<perm_string>::iterator cur = names->begin()
; cur != names->end()
; cur ++ ) {
perm_string txt = *cur;
pform_set_net_range(txt, range, signed_flag, dt);
}
delete names;
if (range)
delete range;
}
/*
* This is invoked to make a named event. This is the declaration of
* the event, and not necessarily the use of it.
*/
static void pform_make_event(perm_string name, const char*fn, unsigned ln)
{
PEvent*event = new PEvent(name);
event->set_file(fn);
event->set_lineno(ln);
pform_cur_module->events[name] = event;
}
void pform_make_events(list<perm_string>*names, const char*fn, unsigned ln)
{
list<perm_string>::iterator cur;
for (cur = names->begin() ; cur != names->end() ; cur++) {
perm_string txt = *cur;
pform_make_event(txt, fn, ln);
}
delete names;
}
/*
* pform_makegates is called when a list of gates (with the same type)
* are ready to be instantiated. The function runs through the list of
* gates and calls the pform_makegate function to make the individual gate.
*/
void pform_makegate(PGBuiltin::Type type,
struct str_pair_t str,
svector<PExpr*>* delay,
const lgate&info,
svector<named_pexpr_t*>*attr)
{
if (info.parms_by_name) {
cerr << info.file << ":" << info.lineno << ": Gates do not "
"have port names." << endl;
error_count += 1;
return;
}
perm_string dev_name = lex_strings.make(info.name);
PGBuiltin*cur = new PGBuiltin(type, dev_name, info.parms, delay);
if (info.range[0])
cur->set_range(info.range[0], info.range[1]);
if (attr) {
for (unsigned idx = 0 ; idx < attr->count() ; idx += 1) {
named_pexpr_t*tmp = (*attr)[idx];
cur->attributes[tmp->name] = tmp->parm;
}
}
cur->strength0(str.str0);
cur->strength1(str.str1);
cur->set_file(info.file);
cur->set_lineno(info.lineno);
if (pform_cur_generate)
pform_cur_generate->add_gate(cur);
else
pform_cur_module->add_gate(cur);
}
void pform_makegates(PGBuiltin::Type type,
struct str_pair_t str,
svector<PExpr*>*delay,
svector<lgate>*gates,
svector<named_pexpr_t*>*attr)
{
for (unsigned idx = 0 ; idx < gates->count() ; idx += 1) {
pform_makegate(type, str, delay, (*gates)[idx], attr);
}
if (attr) {
for (unsigned idx = 0 ; idx < attr->count() ; idx += 1) {
named_pexpr_t*cur = (*attr)[idx];
delete cur;
}
delete attr;
}
delete gates;
}
/*
* A module is different from a gate in that there are different
* constraints, and sometimes different syntax. The X_modgate
* functions handle the instantiations of modules (and UDP objects) by
* making PGModule objects.
*
* The first pform_make_modgate handles the case of a module
* instantiated with ports passed by position. The "wires" is an
* ordered array of port expressions.
*
* The second pform_make_modgate handles the case of a module
* instantiated with ports passed by name. The "bind" argument is the
* ports matched with names.
*/
static void pform_make_modgate(perm_string type,
perm_string name,
struct parmvalue_t*overrides,
svector<PExpr*>*wires,
PExpr*msb, PExpr*lsb,
const char*fn, unsigned ln)
{
PGModule*cur = new PGModule(type, name, wires);
cur->set_file(fn);
cur->set_lineno(ln);
cur->set_range(msb,lsb);
if (overrides && overrides->by_name) {
unsigned cnt = overrides->by_name->count();
named<PExpr*>*byname = new named<PExpr*>[cnt];
for (unsigned idx = 0 ; idx < cnt ; idx += 1) {
named_pexpr_t*curp = (*overrides->by_name)[idx];
byname[idx].name = curp->name;
byname[idx].parm = curp->parm;
}
cur->set_parameters(byname, cnt);
} else if (overrides && overrides->by_order) {
cur->set_parameters(overrides->by_order);
}
if (pform_cur_generate)
pform_cur_generate->add_gate(cur);
else
pform_cur_module->add_gate(cur);
}
static void pform_make_modgate(perm_string type,
perm_string name,
struct parmvalue_t*overrides,
svector<named_pexpr_t*>*bind,
PExpr*msb, PExpr*lsb,
const char*fn, unsigned ln)
{
unsigned npins = bind->count();
named<PExpr*>*pins = new named<PExpr*>[npins];
for (unsigned idx = 0 ; idx < npins ; idx += 1) {
named_pexpr_t*curp = (*bind)[idx];
pins[idx].name = curp->name;
pins[idx].parm = curp->parm;
}
PGModule*cur = new PGModule(type, name, pins, npins);
cur->set_file(fn);
cur->set_lineno(ln);
cur->set_range(msb,lsb);
if (overrides && overrides->by_name) {
unsigned cnt = overrides->by_name->count();
named<PExpr*>*byname = new named<PExpr*>[cnt];
for (unsigned idx = 0 ; idx < cnt ; idx += 1) {
named_pexpr_t*curp = (*overrides->by_name)[idx];
byname[idx].name = curp->name;
byname[idx].parm = curp->parm;
}
cur->set_parameters(byname, cnt);
} else if (overrides && overrides->by_order) {
cur->set_parameters(overrides->by_order);