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examples updated FSF-address Aug 29, 2012
ivlpp Update flex destroy routines to work for version 2.6 and greater Nov 17, 2017
libmisc Fix for GitHub issue #162 : very wide busses cause assertion failure. Sep 11, 2017
libveriuser Add cppcheck suppressions for libveriuser Dec 20, 2015
scripts Add the -Wimplicit-dimensions warning. Feb 7, 2016
solaris Drop useless CVS stuff in .txt files Mar 11, 2009
tgt-blif Implement barrel shifter LPM for BLIF target Jun 13, 2016
tgt-fpga Fix some cppcheck warnings (format string vs argument mismatches) Aug 2, 2014
tgt-null Updated copyright dates displayed for main programs and targets. Aug 17, 2015
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tgt-pcb Update flex destroy routines to work for version 2.6 and greater Nov 17, 2017
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tgt-verilog Add preliminary support for always_comb, always_ff and always_latch Nov 20, 2017
tgt-vhdl Fix for GitHub issue #128 - disable CONCATZ generation for vhdl target. Nov 25, 2016
tgt-vlog95 Add support to convert always_comb/latch to vlog95 Dec 4, 2017
tgt-vvp Add support for rtran switches in vvp. Feb 23, 2018
vhdlpp Don't allow non-vectorable arguments to $signed/$unsigned. May 14, 2018
vpi Update fstapi.c to the latest version Jul 16, 2018
vvp Fix for GitHub issue #198 - support octal display for thread variables. Jun 12, 2018
.gitattributes Attempt to allow native line endings in Windows git checkouts. May 1, 2015
.gitignore Initial BLIF code generator. Aug 2, 2013
AStatement.cc updated FSF-address Aug 29, 2012
AStatement.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
Attrib.cc updated FSF-address Aug 29, 2012
Attrib.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
BUGS.txt Spelling fixes Mar 14, 2011
COPYING Update COPYING to match FSF version and update tgt-vlog95/Makefile.in Apr 19, 2013
COPYING.lesser vlog95: Add a copyright notice for the Icarus UDPs and print a note. Mar 1, 2011
HName.cc Have scope auto-rename generate names that use the index numbers Sep 30, 2015
HName.h Have scope auto-rename generate names that use the index numbers Sep 30, 2015
INSTALL autoconf the makefiles. Apr 25, 1999
Makefile.in Renamed synthsplit to exposenodes. Feb 27, 2016
Module.cc Rework handling of timescales in parser. Nov 5, 2017
Module.h Rework handling of timescales in parser. Nov 5, 2017
PClass.cc Elaborate PChainConstructor calls. Nov 11, 2013
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PDelays.cc Factor out common code for warning about inconsistent timescales. Nov 5, 2017
PDelays.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
PEvent.cc updated FSF-address Aug 29, 2012
PEvent.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
PExpr.cc Fix for GitHub issue #94 - enhance support for SystemVerilog size cas… Mar 25, 2016
PExpr.h Fix for GitHub issue #94 - enhance support for SystemVerilog size cas… Mar 25, 2016
PFunction.cc Implement $bits(type) to get the size of a type Jan 12, 2014
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PGenerate.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
PModport.cc Added parser support for SV modport declarations. Jan 10, 2015
PModport.h Added parser support for SV modport declarations. Jan 10, 2015
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PScope.h Rework handling of timescales in parser. Nov 5, 2017
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PTask.h Add check for explicit lifetime when initialising static variables. Mar 19, 2016
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PUdp.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
PWire.cc Generalize user defined function return type handling. Apr 20, 2013
PWire.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
QUICK_START.txt Clean up spurious trailing white space. Oct 4, 2004
README.txt Fixed install step misnomer in README Mar 28, 2018
Statement.cc Add preliminary support for always_comb, always_ff and always_latch Nov 20, 2017
Statement.h Add preliminary support for always_comb, always_ff and always_latch Nov 20, 2017
_pli_types.h.in Update header files to use a more standard name to prevent rereading Jul 23, 2014
acc_user.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
aclocal.m4 Fix x86_64-w64-mingw32 build: undefined ___strtod Feb 24, 2017
async.cc nodangle functor accounts for NexusSet links May 8, 2014
attributes.txt Support time0 resolution of combinational threads. Sep 4, 2003
autoconf.sh Basic patch from github #44 Nov 4, 2014
check.conf Fix make check to support -tconf configuration method. Dec 12, 2003
compiler.h First step towards supporting separate compilation units in SV. Oct 31, 2017
config.guess Updated config.guess and config.sub. May 4, 2015
config.h.in GTKWave (fstapi.c) needs realpath() so check for it Dec 19, 2015
config.sub Updated config.guess and config.sub. May 4, 2015
configure.in GTKWave (fstapi.c) needs realpath() so check for it Dec 19, 2015
constants.vams Non-controversial whitespace cleanup Sep 5, 2008
cppcheck.sup Update cppcheck waiver files Oct 23, 2017
cprop.cc Fix errors in constant propagation. Oct 26, 2013
cygwin.txt Clean up spurious trailing white space. Oct 4, 2004
design_dump.cc Add preliminary support for always_comb, always_ff and always_latch Nov 20, 2017
developer-quick-start.txt Touch up new developer quick start Nov 1, 2008
discipline.cc updated FSF-address Aug 29, 2012
discipline.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
disciplines.vams Nature and discipline declarations syntax May 11, 2008
dosify.c More spelling, comments only Apr 1, 2016
dup_expr.cc Add support for dynamic array/queue "last" index ($) Aug 21, 2014
elab_anet.cc updated FSF-address Aug 29, 2012
elab_expr.cc Don't allow non-vectorable arguments to $signed/$unsigned. May 14, 2018
elab_lval.cc Fix some cppcheck warning issues Sep 14, 2016
elab_net.cc ivl: Support for part selection in multidimensional packed ports assi… Mar 7, 2016
elab_scope.cc Rework handling of timescales in parser. Nov 5, 2017
elab_sig.cc Support separate compilation units in SystemVerilog. Oct 31, 2017
elab_sig_analog.cc updated FSF-address Aug 29, 2012
elab_type.cc Support separate compilation units in SystemVerilog. Oct 31, 2017
elaborate.cc Enable variable declarations/initialisations in the compilation unit … Feb 18, 2018
elaborate_analog.cc Remove some cppcheck warnings, etc. Nov 13, 2012
emit.cc Support separate compilation units in SystemVerilog. Oct 31, 2017
eval.cc Add support for power operator in eval_const() Jul 8, 2014
eval_attrib.cc updated FSF-address Aug 29, 2012
eval_tree.cc Add support for the wild compare operators ==? and !=? Nov 18, 2017
exposenodes.cc Fix space issues. Feb 29, 2016
expr_synth.cc Add some synthesis checks for the always_comb/ff/latch blocks Dec 27, 2017
extensions.txt Spelling fixes Jan 30, 2008
functor.cc NetLatch class Mar 11, 2016
functor.h NetLatch class Mar 11, 2016
glossary.txt Add the glossary file. May 15, 2001
ieee1364-notes.txt Spelling and related fixes Apr 27, 2011
install-sh Clean up spurious trailing white space. Oct 4, 2004
iverilog-vpi.man.in Add library search path option to iverilog-vpi (GitHub issue #145). Jan 29, 2017
iverilog-vpi.sh Add the --ccflags option to iverilog-vpi Apr 11, 2018
ivl.def Pass to the targets if an implicit T0 trigger event is needed. Dec 4, 2017
ivl_alloc.h Changes for ivl_alloc.h Jul 22, 2015
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ivl_target.h Pass to the targets if an implicit T0 trigger event is needed. Dec 4, 2017
ivl_target.txt Drop useless CVS stuff in .txt files Mar 11, 2009
ivl_target_priv.h Support separate compilation units in SystemVerilog. Oct 31, 2017
lexor.lex Add support for the wild compare operators ==? and !=? Nov 18, 2017
lexor_keyword.gperf Basic patch from github #44 Nov 4, 2014
lexor_keyword.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
link_const.cc Enhanced support for asynchronous set/reset in synthesis. Feb 21, 2016
load_module.cc First step towards supporting separate compilation units in SV. Oct 31, 2017
lpm.txt Spelling fixes. Jan 30, 2003
macosx.txt Remove more CVS stuff Aug 16, 2012
main.cc Include compilation units in pform dump. Feb 18, 2018
mingw.txt Remove outdated instructions in mingw.txt and point to the Wiki instead. May 10, 2015
mkinstalldirs Update mkinstalldirs to handle paths with spaces. Feb 4, 2009
named.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
net_analog.cc updated FSF-address Aug 29, 2012
net_assign.cc Fix expression type for compressed assignment statements. Feb 23, 2016
net_design.cc Support separate compilation units in SystemVerilog. Oct 31, 2017
net_event.cc Add some synthesis checks for the always_comb/ff/latch blocks Dec 27, 2017
net_expr.cc Get arrayed property expressions down to the ivl_target API. Sep 16, 2014
net_func.cc Non-method tasks/functions support default arguments. Sep 21, 2013
net_func_eval.cc Fully support variable initialization in tasks/functions/named blocks. Mar 19, 2016
net_link.cc Synthesis rework. Feb 21, 2016
net_modulo.cc updated FSF-address Aug 29, 2012
net_nex_input.cc Add some synthesis checks for the always_comb/ff/latch blocks Dec 27, 2017
net_nex_output.cc Add some synthesis checks for the always_comb/ff/latch blocks Dec 27, 2017
net_proc.cc Fully support variable initialization in tasks/functions/named blocks. Mar 19, 2016
net_scope.cc Fix shadow warning when using older versions of gcc. Nov 8, 2017
net_tran.cc updated FSF-address Aug 29, 2012
net_udp.cc updated FSF-address Aug 29, 2012
netclass.cc Enable base class tasks to be used in an extended class. Oct 8, 2017
netclass.h Add support for classes defined in $root scope. Sep 16, 2014
netdarray.cc Handle array assignment patters through pform. Oct 19, 2013
netdarray.h A dynamic array can have a signed type so pass that correctly Mar 2, 2015
netenum.cc Enumerations are compatible if their type definitions match. Nov 4, 2014
netenum.h Enumerations are compatible if their type definitions match. Nov 4, 2014
netlist.cc The synth check needs to check the task scope Dec 28, 2017
netlist.h Check system/user tasks for always_comb/ff/latch synth. Dec 28, 2017
netlist.txt updated FSF-address Aug 29, 2012
netmisc.cc Add support for the wild compare operators ==? and !=? Nov 18, 2017
netmisc.h Factor out common code for warning about inconsistent timescales. Nov 5, 2017
netparray.cc Work towards nested packed struct member vectors. Dec 23, 2014
netparray.h Work towards nested packed struct member vectors. Dec 23, 2014
netqueue.cc Support declaring queue variables all the way to vvp. Aug 21, 2014
netqueue.h A SV queue can be signed. Mar 8, 2015
netscalar.cc Handle strings as class object properties. Jan 28, 2013
netscalar.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
netstruct.cc Handle enumerations as packed struct/union members. Dec 7, 2013
netstruct.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
nettypes.cc Fix for GitHub issue 112 - index calculation for >2D packed arrays. Jul 9, 2016
nettypes.h Spelling fixes Apr 13, 2015
netvector.cc Generalize struct member type Dec 7, 2013
netvector.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
nodangle.cc Spelling and whitespace Mar 14, 2016
pad_to_width.cc Refactor to use new pad_to_width/cast_to_width functions. Mar 25, 2016
parse.y Improved check for missing task/function port direction. Feb 21, 2018
parse_api.h Support separate compilation units in SystemVerilog. Oct 31, 2017
parse_misc.cc Add a couple missing va_end() calls Sep 5, 2014
parse_misc.h Rework handling of timescales in parser. Nov 5, 2017
pform.cc Enable parameter/localparameter definitions in the compilation unit s… Feb 18, 2018
pform.h Output an error message when a SV variable declaration reuses a name. Feb 18, 2018
pform_analog.cc updated FSF-address Aug 29, 2012
pform_class_type.cc Output an error message when a SV variable declaration reuses a name. Feb 18, 2018
pform_disciplines.cc updated FSF-address Aug 29, 2012
pform_dump.cc Enable variable declarations/initialisations in the compilation unit … Feb 18, 2018
pform_package.cc Added support for default subroutine lifetimes (SystemVerilog). Mar 19, 2016
pform_pclass.cc Fix for br1005 - segfault when SV queue is declared inside a class. Jul 11, 2016
pform_string_type.cc Output an error message when a SV variable declaration reuses a name. Feb 18, 2018
pform_struct_type.cc Output an error message when a SV variable declaration reuses a name. Feb 18, 2018
pform_types.cc Elaborate foreach loops as synthetic for loops. Aug 21, 2014
pform_types.h Fix for br974 - support SV types in non-ansi port declarations. Apr 4, 2016
property_qual.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
sv_vpi_user.h Merge branch 'master' into return-stack Feb 1, 2016
svector.h A few updates based on cppcheck results Oct 23, 2017
swift.txt Spelling fixes. Jul 15, 2003
symbol_search.cc Support separate compilation units in SystemVerilog. Oct 31, 2017
syn-rules.y Note the always_comb/ff/latch have not been looked at for synthesis Dec 4, 2017
sync.cc nodangle functor accounts for NexusSet links May 8, 2014
synth.cc Add preliminary support for always_comb, always_ff and always_latch Nov 20, 2017
synth2.cc Fix for GitHub issue #115 - synthesis aborts on case with max guard o… Jul 22, 2016
sys_funcs.cc ivl & vvp: Enabled 'string' as the return type in VPI functions. Jan 5, 2016
t-dll-analog.cc updated FSF-address Aug 29, 2012
t-dll-api.cc Pass to the targets if an implicit T0 trigger event is needed. Dec 4, 2017
t-dll-expr.cc More spelling, comments only Apr 1, 2016
t-dll-proc.cc Pass to the targets if an implicit T0 trigger event is needed. Dec 4, 2017
t-dll.cc Add support for the wild compare operators ==? and !=? Nov 18, 2017
t-dll.h Pass to the targets if an implicit T0 trigger event is needed. Dec 4, 2017
t-dll.txt Spelling and related fixes Apr 27, 2011
target.cc Updated copyright notices. Mar 11, 2016
target.h Updated copyright notices. Mar 11, 2016
util.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
va_math.txt Remove obsolete VAMS $log function. Apr 27, 2010
verilog.spec vhdlpp: std.textio & ieee.std_logic_textio functions implemented usin… Nov 24, 2015
verinum.cc Fix for GitHub issue #199: handle signed division overflow. Jun 12, 2018
verinum.h Make a few constructors explicit. Oct 22, 2015
verireal.cc updated FSF-address Aug 29, 2012
verireal.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
veriuser.h Update header files to use a more standard name to prevent rereading Jul 23, 2014
version.c Fix some cppcheck warnings and bugs Dec 20, 2015
version_base.h Switch devel branch to version 11. Aug 15, 2015
vpi.txt Document VPI_TRACE tracing. Mar 14, 2003
vpi_user.h Use fwrite to write $display output, instead of fprintf Jun 3, 2015
xilinx-hint.txt Spelling fixes. Jan 30, 2003

README.txt

		THE ICARUS VERILOG COMPILATION SYSTEM
		Copyright 2000-2004 Stephen Williams


1.0 What is ICARUS Verilog?

Icarus Verilog is intended to compile ALL of the Verilog HDL as
described in the IEEE-1364 standard. Of course, it's not quite there
yet. It does currently handle a mix of structural and behavioral
constructs. For a view of the current state of Icarus Verilog, see its
home page at <http://iverilog.icarus.com/>.

Icarus Verilog is not aimed at being a simulator in the traditional
sense, but a compiler that generates code employed by back-end
tools.

    For instructions on how to run Icarus Verilog,
    see the ``iverilog'' man page.


2.0 Building/Installing Icarus Verilog From Source

If you are starting from source, the build process is designed to be
as simple as practical. Someone basically familiar with the target
system and C/C++ compilation should be able to build the source
distribution with little effort. Some actual programming skills are
not required, but helpful in case of problems.

If you are building for Windows, see the mingw.txt file.

2.1 Compile Time Prerequisites

You need the following software to compile Icarus Verilog from source
on a UNIX-like system:

	- GNU Make
	  The Makefiles use some GNU extensions, so a basic POSIX
	  make will not work. Linux systems typically come with a
	  satisfactory make. BSD based systems (i.e., NetBSD, FreeBSD)
	  typically have GNU make as the gmake program.

	- ISO C++ Compiler
	  The ivl and ivlpp programs are written in C++ and make use
	  of templates and some of the standard C++ library. egcs and
	  recent gcc compilers with the associated libstdc++ are known
	  to work. MSVC++ 5 and 6 are known to definitely *not* work.

	- bison and flex

	- gperf 2.7
	  The lexical analyzer doesn't recognize keywords directly,
	  but instead matches symbols and looks them up in a hash
	  table in order to get the proper lexical code. The gperf
	  program generates the lookup table.

	  A version problem with this program is the most common cause
	  of difficulty. See the Icarus Verilog FAQ.

	- readline 4.2
	  On Linux systems, this usually means the readline-devel
	  rpm. In any case, it is the development headers of readline
	  that are needed.

	- termcap
	  The readline library in turn uses termcap.

If you are building from git, you will also need software to generate
the configure scripts.

	- autoconf 2.53
	  This generates configure scripts from configure.in. The 2.53
	  or later versions are known to work, autoconf 2.13 is
	  reported to *not* work.

2.2 Compilation

Unpack the tar-ball and cd into the verilog-######### directory
(presumably that is how you got to this README) and compile the source
with the commands:
	
  ./configure
  make

If you are building from git, you have to run the command below before
compile the source. This will generate the "configure" file, which is 
automatically done when building from tarball.

  sh autoconf.sh

Normally, this command automatically figures out everything it needs
to know. It generally works pretty well. There are a few flags to the
configure script that modify its behavior:

	--prefix=<root>
	    The default is /usr/local, which causes the tool suite to
	    be compiled for install in /usr/local/bin,
	    /usr/local/share/ivl, etc.

	    I recommend that if you are configuring for precompiled
	    binaries, use --prefix=/usr.  On Solaris systems, it is
	    common to use --prefix=/opt.  You can configure for a non-root
	    install with --prefix=$HOME.

	--enable-suffix
	--enable-suffix=<your-suffix>
	--disable-suffix
	    Enable/disable changing the names of install files to use
	    a suffix string so that this version or install can co-
	    exist with other versions. This renames the installed
	    commands (iverilog, iverilog-vpi, vvp) and the installed
	    library files and include directory so that installations
	    with the same prefix but different suffix are guaranteed
	    to not interfere with each other.

2.3 (Optional) Testing

To run a simple test before installation, execute

  make check

The commands printed by this run might help you in running Icarus
Verilog on your own Verilog sources before the package is installed
by root.

2.4 Installation

Now install the files in an appropriate place. (The makefiles by
default install in /usr/local unless you specify a different prefix
with the --prefix=<path> flag to the configure command.) You may need
to do this as root to gain access to installation directories.

  make install

2.5 Uninstallation

The generated Makefiles also include the uninstall target. This should
remove all the files that ``make install'' creates.

3.0 How Icarus Verilog Works

This tool includes a parser which reads in Verilog (plus extensions)
and generates an internal netlist. The netlist is passed to various
processing steps that transform the design to more optimal/practical
forms, then is passed to a code generator for final output. The
processing steps and the code generator are selected by command line
switches.

3.1 Preprocessing

There is a separate program, ivlpp, that does the preprocessing. This
program implements the `include and `define directives producing
output that is equivalent but without the directives. The output is a
single file with line number directives, so that the actual compiler
only sees a single input file. See ivlpp/ivlpp.txt for details.

3.2 Parse

The Verilog compiler starts by parsing the Verilog source file. The
output of the parse is a list of Module objects in "pform". The pform
(see pform.h) is mostly a direct reflection of the compilation
step. There may be dangling references, and it is not yet clear which
module is the root.

One can see a human readable version of the final pform by using the
``-P <path>'' flag to the ``ivl'' subcommand. This will cause ivl
to dump the pform into the file named <path>. (Note that this is not
normally done, unless debugging the ``ivl'' subcommand.)

3.3 Elaboration

This phase takes the pform and generates a netlist. The driver selects
(by user request or lucky guess) the root module to elaborate,
resolves references and expands the instantiations to form the design
netlist. (See netlist.txt.) Final semantic checks are performed during
elaboration, and some simple optimizations are performed. The netlist
includes all the behavioral descriptions, as well as gates and wires.

The elaborate() function performs the elaboration.

One can see a human readable version of the final, elaborated and
optimized netlist by using the ``-N <path>'' flag to the compiler. If
elaboration succeeds, the final netlist (i.e., after optimizations but
before code generation) will be dumped into the file named <path>.

Elaboration is actually performed in two steps: scopes and parameters
first, followed by the structural and behavioral elaboration.

3.3.1 Scope Elaboration

This pass scans through the pform looking for scopes and parameters. A
tree of NetScope objects is built up and placed in the Design object,
with the root module represented by the root NetScope object. The
elab_scope.cc file contains most of the code for handling this phase.

The tail of the elaborate_scope behavior (after the pform is
traversed) includes a scan of the NetScope tree to locate defparam
assignments that were collected during scope elaboration. This is when
the defparam overrides are applied to the parameters.

3.3.2 Netlist Elaboration

After the scopes and parameters are generated and the NetScope tree
fully formed, the elaboration runs through the pform again, this time
generating the structural and behavioral netlist. Parameters are
elaborated and evaluated by now so all the constants of code
generation are now known locally, so the netlist can be generated by
simply passing through the pform.

3.4 Optimization

This is actually a collection of processing steps that perform
optimizations that do not depend on the target technology. Examples of
some useful transformations are

	- eliminate null effect circuitry
	- combinational reduction
	- constant propagation

The actual functions performed are specified on the ivl command line by
the -F flags (see below).

3.5 Code Generation

This step takes the design netlist and uses it to drive the code
generator (see target.h). This may require transforming the
design to suit the technology.

The emit() method of the Design class performs this step. It runs
through the design elements, calling target functions as need arises
to generate actual output.

The user selects the target code generator with the -t flag on the
command line.

3.6 ATTRIBUTES

    NOTE: The $attribute syntax will soon be deprecated in favor of the
    Verilog-2001 attribute syntax, which is cleaner and standardized.

The parser accepts, as an extension to Verilog, the $attribute module
item. The syntax of the $attribute item is:

	$attribute (<identifier>, <key>, <value>);

The $attribute keyword looks like a system task invocation. The
difference here is that the parameters are more restricted than those
of a system task. The <identifier> must be an identifier. This will be
the item to get an attribute. The <key> and <value> are strings, not
expressions, that give the key and the value of the attribute to be
attached to the identified object.

Attributes are [<key> <value>] pairs and are used to communicate with
the various processing steps. See the documentation for the processing
step for a list of the pertinent attributes.

Attributes can also be applied to gate types. When this is done, the
attribute is given to every instantiation of the primitive. The syntax
for the attribute statement is the same, except that the <identifier>
names a primitive earlier in the compilation unit and the statement is
placed in global scope, instead of within a module. The semicolon is
not part of a type attribute.

Note that attributes are also occasionally used for communication
between processing steps. Processing steps that are aware of others
may place attributes on netlist objects to communicate information to
later steps.

Icarus Verilog also accepts the Verilog 2001 syntax for
attributes. They have the same general meaning as with the $attribute
syntax, but they are attached to objects by position instead of by
name. Also, the key is a Verilog identifier instead of a string.

4.0 Running iverilog

The preferred way to invoke the compiler is with the iverilog(1)
command. This program invokes the preprocessor (ivlpp) and the
compiler (ivl) with the proper command line options to get the job
done in a friendly way. See the iverilog(1) man page for usage details.


4.1 EXAMPLES

Example: Compiling "hello.vl"

------------------------ hello.vl ----------------------------
module main();

initial
  begin
    $display("Hi there");
    $finish ;
  end

endmodule

--------------------------------------------------------------

Ensure that "iverilog" is on your search path, and the vpi library
is available.

To compile the program:

  iverilog hello.vl

(The above presumes that /usr/local/include and /usr/local/lib are
part of the compiler search path, which is usually the case for gcc.)

To run the program:

  ./a.out

You can use the "-o" switch to name the output command to be generated
by the compiler. See the iverilog(1) man page.

5.0 Unsupported Constructs

Icarus Verilog is in development - as such it still only supports a
(growing) subset of Verilog.  Below is a description of some of the
currently unsupported Verilog features. This list is not exhaustive,
and does not account for errors in the compiler. See the Icarus
Verilog web page for the current state of support for Verilog, and in
particular, browse the bug report database for reported unsupported
constructs.

  - System functions are supported, but the return value is a little
    tricky. See SYSTEM FUNCTION TABLE FILES in the iverilog man page.

  - Specify blocks are parsed but ignored in general.

  - trireg is not supported. tri0 and tri1 are supported.

  - tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1
    and rtranif0 are not supported.

  - Net delays, of the form "wire #N foo;" do not work. Delays in
    every other context do work properly, including the V2001 form
    "wire #5 foo = bar;"

  - Event controls inside non-blocking assignments are not supported.
    i.e.: a <= @(posedge clk) b;

  - Macro arguments are not supported. `define macros are supported,
    but they cannot take arguments.

5.1 Nonstandard Constructs or Behaviors

Icarus Verilog includes some features that are not part of the
IEEE1364 standard, but have well defined meaning, and also sometimes
gives nonstandard (but extended) meanings to some features of the
language that are defined. See the "extensions.txt" documentation for
more details.

    $is_signed(<expr>)
	This system function returns 1 if the expression contained is
	signed, or 0 otherwise. This is mostly of use for compiler
	regression tests.

    $sizeof(<expr>)
    $bits(<expr>)
	The $bits system function returns the size in bits of the
	expression that is its argument. The result of this
	function is undefined if the argument doesn't have a
	self-determined size.

	The $sizeof function is deprecated in favor of $bits, which is
	the same thing, but included in the SystemVerilog definition.

    $simtime
	The $simtime system function returns as a 64bit value the
	simulation time, unscaled by the time units of local
	scope. This is different from the $time and $stime functions
	which return the scaled times. This function is added for
	regression testing of the compiler and run time, but can be
	used by applications who really want the simulation time.

	Note that the simulation time can be confusing if there are
	lots of different `timescales within a design. It is not in
	general possible to predict what the simulation precision will
	turn out to be.

    $mti_random()
    $mti_dist_uniform
	These functions are similar to the IEEE1364 standard $random
	functions, but they use the Mersenne Twister (MT19937)
	algorithm. This is considered an excellent random number
	generator, but does not generate the same sequence as the
	standardized $random.

    Builtin system functions

	Certain of the system functions have well defined meanings, so
	can theoretically be evaluated at compile time, instead of
	using runtime VPI code. Doing so means that VPI cannot
	override the definitions of functions handled in this
	manner. On the other hand, this makes them synthesizable, and
	also allows for more aggressive constant propagation. The
	functions handled in this manner are:

		$bits
		$signed
		$sizeof
		$unsigned

	Implementations of these system functions in VPI modules will
	be ignored.

    Preprocessing Library Modules

	Icarus Verilog does preprocess modules that are loaded from
	libraries via the -y mechanism. However, the only macros
	defined during compilation of that file are those that it
	defines itself (or includes) or that are defined on the
	command line or command file.

	Specifically, macros defined in the non-library source files
	are not remembered when the library module is loaded. This is
	intentional. If it were otherwise, then compilation results
	might vary depending on the order that libraries are loaded,
	and that is too unpredictable.

	It is said that some commercial compilers do allow macro
	definitions to span library modules. That's just plain weird.

    Width in %t Time Formats

	Standard Verilog does not allow width fields in the %t formats
	of display strings. For example, this is illegal:

		$display("Time is %0t", %time);

	Standard Verilog instead relies on the $timeformat to
	completely specify the format.

	Icarus Verilog allows the programmer to specify the field
	width. The "%t" format in Icarus Verilog works exactly as it
	does in standard Verilog. However, if the programmer chooses
	to specify a minimum width (i.e., "%5t"), then for that display
	Icarus Verilog will override the $timeformat minimum width and
	use the explicit minimum width.

    vpiScope iterator on vpiScope objects.

	In the VPI, the normal way to iterate over vpiScope objects
	contained within a vpiScope object, is the vpiInternalScope
	iterator. Icarus Verilog adds support for the vpiScope
	iterator of a vpiScope object, that iterates over *everything*
	the is contained in the current scope. This is useful in cases
	where one wants to iterate over all the objects in a scope
	without iterating over all the contained types explicitly.

    time 0 race resolution.

	Combinational logic is routinely modeled using always
	blocks. However, this can lead to race conditions if the
	inputs to the combinational block are initialized in initial
	statements. Icarus Verilog slightly modifies time 0 scheduling
	by arranging for always statements with ANYEDGE sensitivity
	lists to be scheduled before any other threads. This causes
	combinational always blocks to be triggered when the values in
	the sensitivity list are initialized by initial threads.

    Nets with Types

	Icarus Verilog support an extension syntax that allows nets
	and regs to be explicitly typed. The currently supported types
	are logic, bool and real. This implies that "logic" and "bool"
	are new keywords. Typical syntax is:

	wire real foo = 1.0;
	reg logic bar, bat;

	... and so forth. The syntax can be turned off by using the
	-g2 flag to iverilog, and turned on explicitly with the -g2x
	flag to iverilog.

6.0 CREDITS

Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
Copyright Stephen Williams. The proper notices are in the head of each
file. However, I have early on received aid in the form of fixes,
Verilog guidance, and especially testing from many people. Testers in
particular include a larger community of people interested in a GPL
Verilog for Linux.