PSL property analysis fails when braces around it are missing

[Blebowski]

Hi,

trying to analyze following code:

library ieee;
use ieee.std_logic_1164.all;

entity psl_braces_missing is
end entity;

architecture tb of psl_braces_missing is

    signal clk : std_logic;

    signal a,b : std_logic;

begin

    -- psl default clock is rising_edge(clk);

    -- psl asrt_1 : assert always
    --  a -> b
    --  report "HALOO";

end architecture;

errors out with:

** Error: unexpected end while parsing assert directive, expecting one of **, union or ;
    > psl_braces_missing.vhd:21
    |
 21 | end architecture;
    | ^^^ this token was unexpected

If I wrap the a -> b into braces:

 -- psl asrt_1 : assert always
    --  (a -> b)
    --  report "HALOO";

the code analyses without problems.
If I try both versions in Aldec, it analyzes without problems.