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vm_instructions.h
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vm_instructions.h
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#ifndef VM_LICENSE
#define VM_LICENSE(ARGS...)
#endif
VM_LICENSE(
"Copyright (c) 2013 Noel Raymond Cower.",
"",
"This file is part of Rusalka VM.",
"",
"Rusalka VM is free software: you can redistribute it and/or modify",
" it under the terms of the GNU General Public License as published by",
" the Free Software Foundation, either version 3 of the License, or",
" (at your option) any later version.",
"",
"Rusalka VM is distributed in the hope that it will be useful,",
" but WITHOUT ANY WARRANTY; without even the implied warranty of",
" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the",
" GNU General Public License for more details.",
"",
"You should have received a copy of the GNU General Public License",
" along with Rusalka VM. If not, see <http://www.gnu.org/licenses/>."
)
INSTRUCTION( NOP, NOP, 0, 0 )
INSTRUCTION( ADD_F32, FADD, 1, 3, reg(f32, output), reg(f32, input), reg(f32, input) )
INSTRUCTION( ADD_I32, ADD, 2, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( ADD_UI32, UADD, 3, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( ADD_F32_L, FADDL, 4, 3, reg(f32, output), reg(f32, input), f32 )
INSTRUCTION( ADD_I32_L, ADDL, 5, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( ADD_UI32_L, UADDL, 6, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( SUB_F32, FSUB, 7, 3, reg(f32, output), reg(f32, input), reg(f32, input) )
INSTRUCTION( SUB_I32, SUB, 8, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( SUB_UI32, USUB, 9, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( SUB_F32_L, FSUBL, 10, 3, reg(f32, output), reg(f32, input), f32 )
INSTRUCTION( SUB_I32_L, SUBL, 11, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( SUB_UI32_L, USUBL, 12, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( DIV_F32, FDIV, 13, 3, reg(f32, output), reg(f32, input), reg(f32, input) )
INSTRUCTION( DIV_I32, DIV, 14, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( DIV_UI32, UDIV, 15, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( DIV_F32_L, FDIVL, 16, 3, reg(f32, output), reg(f32, input), f32 )
INSTRUCTION( DIV_I32_L, DIVL, 17, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( DIV_UI32_L, UDIVL, 18, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( MUL_F32, FMUL, 19, 3, reg(f32, output), reg(f32, input), reg(f32, input) )
INSTRUCTION( MUL_I32, MUL, 20, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( MUL_UI32, UMUL, 21, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( MUL_F32_L, FMULL, 22, 3, reg(f32, output), reg(f32, input), f32 )
INSTRUCTION( MUL_I32_L, MULL, 23, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( MUL_UI32_L, UMULL, 24, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( MOD_F32, FMOD, 25, 3, reg(f32, output), reg(ui32, input), reg(f32, input) )
INSTRUCTION( MOD_I32, MOD, 26, 3, reg(i32, output), reg(ui32, input), reg(i32, input) )
INSTRUCTION( MOD_UI32, UMOD, 27, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( MOD_F32_L, FMODL, 28, 3, reg(f32, output), reg(f32, input), f32 )
INSTRUCTION( MOD_I32_L, MODL, 29, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( MOD_UI32_L, UMODL, 30, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( NEG_F32, FNEG, 31, 2, reg(f32, output), reg(f32, input) )
INSTRUCTION( NEG_I32, NEG, 32, 2, reg(i32, output), reg(i32, input) )
INSTRUCTION( NOT_UI32, UNOT, 33, 2, reg(ui32, output), reg(ui32, input) )
INSTRUCTION( OR_UI32, UOR, 34, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( AND_UI32, UAND, 35, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( XOR_UI32, UXOR, 36, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( SHR_I32, SHR, 37, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( SHR_UI32, USHR, 38, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( SHL_I32, SHL, 39, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( SHL_UI32, USHL, 40, 3, reg(ui32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( OR_UI32_L, UORL, 41, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( AND_UI32_L, UANDL, 42, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( XOR_UI32_L, UXORL, 43, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( SHR_I32_L, SHRL, 44, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( SHR_UI32_L, USHRL, 45, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( SHL_I32_L, SHLL, 46, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( SHL_UI32_L, USHLL, 47, 3, reg(ui32, output), reg(ui32, input), ui32 )
INSTRUCTION( ITOUI, ITOU, 48, 2, reg(i32, output), reg(ui32, input) )
INSTRUCTION( ITOF, ITOF, 49, 2, reg(i32, output), reg(f32, input) )
INSTRUCTION( FTOUI, FTOU, 50, 2, reg(f32, output), reg(ui32, input) )
INSTRUCTION( FTOI, FTOI, 51, 2, reg(f32, output), reg(i32, input) )
INSTRUCTION( UITOF, UTOF, 52, 2, reg(ui32, output), reg(f32, input) )
INSTRUCTION( UITOI, UTOI, 53, 2, reg(ui32, output), reg(i32, input) )
INSTRUCTION( CMP_F32, FCMP, 54, 3, reg(i32, output), reg(f32, input), reg(f32, input) )
INSTRUCTION( CMP_I32, CMP, 55, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( CMP_UI32, UCMP, 56, 3, reg(i32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( CMP_F32_L, FCMPL, 57, 3, reg(i32, output), reg(f32, input), f32 )
INSTRUCTION( CMP_I32_L, CMPL, 58, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( CMP_UI32_L, UCMPL, 59, 3, reg(i32, output), reg(ui32, input), ui32 )
INSTRUCTION( RCMP_F32, RFCMP, 60, 3, reg(i32, output), reg(f32, input), reg(f32, input) )
INSTRUCTION( RCMP_I32, RCMP, 61, 3, reg(i32, output), reg(i32, input), reg(i32, input) )
INSTRUCTION( RCMP_UI32, RUCMP, 62, 3, reg(i32, output), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( RCMP_F32_L, RFCMPL, 63, 3, reg(i32, output), reg(f32, input), f32 )
INSTRUCTION( RCMP_I32_L, RCMPL, 64, 3, reg(i32, output), reg(i32, input), i32 )
INSTRUCTION( RCMP_UI32_L, RUCMPL, 65, 3, reg(i32, output), reg(ui32, input), ui32 )
INSTRUCTION( JNZ, JNZ, 66, 2, reg(i32, input), reg(i32, input) )
INSTRUCTION( JEZ, JEZ, 67, 2, reg(i32, input), reg(i32, input) )
INSTRUCTION( JGTE, JGTE, 68, 2, reg(i32, input), reg(i32, input) )
INSTRUCTION( JLTE, JLTE, 69, 2, reg(i32, input), reg(i32, input) )
INSTRUCTION( JLT, JLT, 70, 2, reg(i32, input), reg(i32, input) )
INSTRUCTION( JGT, JGT, 71, 2, reg(i32, input), reg(i32, input) )
INSTRUCTION( JUMP, JUMP, 72, 1, reg(i32, input) )
INSTRUCTION( JNZ_L, JNZL, 73, 2, reg(i32, input), i32 )
INSTRUCTION( JEZ_L, JEZL, 74, 2, reg(i32, input), i32 )
INSTRUCTION( JGTE_L, JGTEL, 75, 2, reg(i32, input), i32 )
INSTRUCTION( JLTE_L, JLTEL, 76, 2, reg(i32, input), i32 )
INSTRUCTION( JLT_L, JLTL, 77, 2, reg(i32, input), i32 )
INSTRUCTION( JGT_L, JGTL, 78, 2, reg(i32, input), i32 )
INSTRUCTION( JUMP_L, JUMPL, 79, 1, i32 )
INSTRUCTION( STORE, STORE, 80, 2, reg(i32, input), reg(value, input) )
INSTRUCTION( STORE_L, STOREL, 81, 2, i32, reg(value, input) )
INSTRUCTION( GET, GET, 82, 2, reg(value, output), reg(i32, input) )
INSTRUCTION( GET_L, GETL, 83, 2, reg(value, output), i32 )
INSTRUCTION( PUSH, PUSH, 84, 1, ui32 )
INSTRUCTION( POP, POP, 85, 1, ui32 )
INSTRUCTION( LOAD, LOAD, 86, 2, reg(value, output), value )
INSTRUCTION( MOVE, MOV, 87, 2, reg(value, output), reg(value, input) )
INSTRUCTION( CALL, CALL, 88, 2, i32, ui32 )
INSTRUCTION( CALL_D, CALLD, 89, 2, reg(i32, input), reg(ui32, input) )
INSTRUCTION( RETURN, RETURN, 90, 1, reg(value, input) )
INSTRUCTION( ALLOC, ALLOC, 91, 2, reg(i32, output), reg(ui32, input) )
INSTRUCTION( ALLOC_L, ALLOCL, 92, 2, reg(i32, output), ui32 )
INSTRUCTION( FREE, FREE, 93, 1, reg(i32, input) )
INSTRUCTION( PEEK8, PEEK8, 94, 3, reg(value, output), reg(i32, input), reg(ui32, input) )
INSTRUCTION( PEEK16, PEEK16, 95, 3, reg(value, output), reg(i32, input), reg(ui32, input) )
INSTRUCTION( PEEK32, PEEK32, 96, 3, reg(value, output), reg(i32, input), reg(ui32, input) )
INSTRUCTION( POKE8, POKE8, 97, 3, reg(i32, input), reg(ui32, input), reg(value, input) )
INSTRUCTION( POKE16, POKE16, 98, 3, reg(i32, input), reg(ui32, input), reg(value, input) )
INSTRUCTION( POKE32, POKE32, 99, 3, reg(i32, input), reg(ui32, input), reg(value, input) )
INSTRUCTION( PEEK8_L, PEEK8L, 100, 3, reg(value, output), reg(i32, input), ui32 )
INSTRUCTION( PEEK16_L, PEEK16L, 101, 3, reg(value, output), reg(i32, input), ui32 )
INSTRUCTION( PEEK32_L, PEEK32L, 102, 3, reg(value, output), reg(i32, input), ui32 )
INSTRUCTION( POKE8_L, POKE8L, 103, 3, reg(i32, input), ui32, reg(value, input) )
INSTRUCTION( POKE16_L, POKE16L, 104, 3, reg(i32, input), ui32, reg(value, input) )
INSTRUCTION( POKE32_L, POKE32L, 105, 3, reg(i32, input), ui32, reg(value, input) )
INSTRUCTION( MEMMOVE, MEMMOVE, 106, 5, reg(ui32, input), reg(ui32, input), reg(ui32, input), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( MEMMOVE_L, MEMMOVEL, 107, 5, reg(ui32, input), reg(ui32, input), reg(ui32, input), reg(ui32, input), reg(ui32, input) )
INSTRUCTION( LOGAND, LOGAND, 108, 3, reg(value, output), reg(value, input), reg(value, input) )
INSTRUCTION( LOGOR, LOGOR, 109, 3, reg(value, output), reg(value, input), reg(value, input) )
INSTRUCTION( TRAP, TRAP, 110, 0 )
INSTRUCTION( SWAP, SWAP, 111, 2, reg(value, inout), reg(value, inout) )
INSTRUCTION( MEMDUP, MEMDUP, 112, 2, reg(ui32, output), reg(ui32, input) )
INSTRUCTION( MEMLEN, MEMLEN, 113, 2, reg(ui32, output), reg(ui32, input) )