Integrating Verilog modules to build MIPS and uPOWER Processor pipelines.
Assembler to convert uPOWER assembly instructions into binary, and Simulator to execute the binary uPOWER instructions, both built using Python.
Niranjan S Yadiyala (181CO136)
Rajath C Aralikatti (181CO241)
Varun NR (181CO134)
Shruthan R (181CO250)