gpsign: cfg: sample omap3630 config file

New configuration file added for OMAP 3630 based on zoom3
Usage: a) make
       b) ./gpsign -c configs/sample-3630.cfg -l 80000000 -f u-boot.bin

Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>

README

@@ -290,6 +290,7 @@ operations such as flashing an image etc.. and ease up things a lot more]
 |-- COPYING (Copy Right file ->READ THIS)
 |-- README (This file)
 |-- configs (Sample configuration files for boards)
+|   |-- sample-3630.cfg - sample omap3630 file (example zoom3)
 |   `-- sample.cfg
 |-- docs (documentation Directory)
 |   |-- c1_s1_main.dox

configs/sample-3630.cfg

@@ -0,0 +1,89 @@
+/*
+ *
+ * Sample configuration file for gpsign (e.g. zoom3)
+ *
+ * (C) Copyright 2009
+ * Texas Instruments, <www.ti.com>
+ * Sukumar Ghorai <s-ghorai@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Default image load address when using this config file */
+loadaddr = "0x80000000"
+
+/*
+ * The following section is a MUST HAVE
+ * provides the settings of the clocks etc.
+ */
+platform_chsettings = {
+	section_key = "0xC0C0C0C1"
+	valid = "0x1"
+	version = "0x1"
+	flags = "0x050001FD"
+	/*General clock settings */
+	GEN_PRM_CLKSRC_CTRL = "0x40"
+	GEN_PRM_CLKSEL = "0x3"
+	GEN_CM_CLKSEL1_EMU = "0x2"
+	/* Clock Configuration */
+	CLK_CM_CLKSEL_CORE = "0x130A"
+	CLK_CM_CLKSEL_WKUP = "0x15"
+	/* DPLL3 (Core) Settings */
+	DPLL3_CM_CLKEN_PLL = "0x00370007"
+	DPLL3_CM_AUTOIDLE_PLL = "0x0"
+	DPLL3_CM_CLKSEL1_PLL = "0x08C80C00"
+	/* DPLL4 (Peripheral) Settings */
+	DPLL4_CM_CLKEN_PLL = "0x00000011"
+	DPLL4_CM_AUTOIDLE_PLL = "0x00000000"
+	DPLL4_CM_CLKSEL2_PLL = "0x0441B00C"
+	DPLL4_CM_CLKSEL3_PLL = "0x00000009"
+	/* DPLL1(MPU) Settings */
+	DPLL1_CM_CLKEN_PLL_MPU = "0x00000037"
+	DPLL1_CM_AUTOIDLE_PLL_MPU = "0x0"
+	DPLL1_CM_CLKSEL1_PLL_MPU = "0x00112C0C"
+	DPLL1_CM_CLKSEL2_PLL_MPU = "0x1"
+	DPLL1_CM_CLKSTCTRL_MPU = "0x0"
+}
+
+/* SDRAM configuration section - optional */
+platform_chram = {
+	section_key = "0xC0C0C0C2"
+	valid = "0x1"
+	SDRC_SYSCONFIG_LSB = "0x0000"
+	SDRC_CS_CFG_LSB = "0x0002"
+	SDRC_SHARING_LSB = "0x0100"
+	SDRC_DLLA_CTRL = "0x0000000A"
+	SDRC_POWER = "0x00000085"
+	/* I use CS0 and CS1 */
+	flags = "0x3"
+	/* CS0 */
+	mem_type_cs0 = "0x3"
+	SDRC_MCFG_0 =  "0x03588099"
+	SDRC_MR_0_LSB = "0x00000032"
+	SDRC_ACTIM_CTRLA_0 = "0xA2E1B4C6"
+	SDRC_ACTIM_CTRLB_0 = "0x0002131C"
+	SDRC_RFRCTRL_0 = "0x0005E601"
+	/* CS1 */
+	mem_type_cs1 = "0x3"
+	SDRC_MCFG_1 =  "0x03588099"
+	SDRC_MR_1_LSB = "0x00000032"
+	SDRC_ACTIM_CTRLA_1 = "0xA2E1B4C6"
+	SDRC_ACTIM_CTRLB_1 = "0x0002131C"
+	SDRC_RFRCTRL_1 = "0x0005E601"
+}
+
+/*
+ * Similar structures for platform_chflash and platform_chmmcsd
+ * can optionally exist
+ */