rtl/ram_sdp: Add no_rw_check attribute

This module doesn't define any semantics for R/W at the same address, so tell the synthesis tool to do whatever it wants Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
no2fpga · Jun 11, 2022 · 59350da · 59350da
1 parent f9d1d47
commit 59350da
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/rtl/ram_sdp.v b/rtl/ram_sdp.v
@@ -26,6 +26,7 @@ module ram_sdp #(
 	input  wire clk
 );
 	// Signals
+	(* no_rw_check *)
 	reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
 
 `ifdef SIM