ChronoClock_FPGA_Altera_DE1

Solution of TP1 of the module "Design of SoPC"

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.qsys_edit		.qsys_edit
Software_irq/.metadata		Software_irq/.metadata
TP1_montre/synthesis		TP1_montre/synthesis
db		db
incremental_db		incremental_db
output_files		output_files
software		software
software_irq1/.metadata		software_irq1/.metadata
DE1_pin_assignments.csv		DE1_pin_assignments.csv
LICENSE		LICENSE
README.md		README.md
TP1_montre.bsf		TP1_montre.bsf
TP1_montre.cmp		TP1_montre.cmp
TP1_montre.html		TP1_montre.html
TP1_montre.qpf		TP1_montre.qpf
TP1_montre.qsf		TP1_montre.qsf
TP1_montre.qsf.bak		TP1_montre.qsf.bak
TP1_montre.qsys		TP1_montre.qsys
TP1_montre.qws		TP1_montre.qws
TP1_montre.sopcinfo		TP1_montre.sopcinfo
TP1_montre.vhd		TP1_montre.vhd
TP1_montre_generation.rpt		TP1_montre_generation.rpt
TP1_montre_generation_1.rpt		TP1_montre_generation_1.rpt
TP1_montre_top.vhd		TP1_montre_top.vhd
TP1_montre_top.vhd.bak		TP1_montre_top.vhd.bak
tp1_montre_new.vhd		tp1_montre_new.vhd
tp1_montre_new.vhd.bak		tp1_montre_new.vhd.bak

noureddine-as/ChronoClock_FPGA_Altera_DE1