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Making possible to update SpiceEditor inside AscEditors
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nunobrum committed May 5, 2024
1 parent 0f33c15 commit 1d6f483
Showing 1 changed file with 5 additions and 5 deletions.
10 changes: 5 additions & 5 deletions examples/sim_runner_callback_example.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
RichHandler = None
import PyLTSpice

from PyLTSpice import SimRunner, SpiceEditor
from PyLTSpice import SimRunner, AscEditor
PyLTSpice.set_log_level(logging.DEBUG)
if RichHandler:
PyLTSpice.add_log_handler(RichHandler())
Expand All @@ -26,13 +26,13 @@ def processing_data(raw_file, log_file):
runner = SimRunner(output_folder='./temp_batch3') # Configures the simulator to use and output
# folder

netlist = SpiceEditor("./testfiles/Batch_Test.asc") # Open the Spice Model, and creates the .net
netlist = AscEditor("./testfiles/Batch_Test.asc") # Open the Spice Model, and creates the .net
# set default arguments
netlist.set_parameters(res=0, cap=100e-6)
netlist.set_component_value('R2', '2k') # Modifying the value of a resistor
netlist.set_component_value('R1', '4k')
netlist.set_element_model('V3', "SINE(0 1 3k 0 0 0)") # Modifying the
netlist.set_component_value('XU1:C2', 20e-12) # modifying a
netlist.set_component_value('U1:C2', 20e-12) # modifying a
# define simulation
netlist.add_instructions(
"; Simulation settings",
Expand All @@ -43,12 +43,12 @@ def processing_data(raw_file, log_file):
use_run_now = False

for opamp in ('AD712', 'AD820'):
netlist.set_element_model('XU1', opamp)
netlist.set_element_model('U1', opamp)
for supply_voltage in (5, 10, 15):
netlist.set_component_value('V1', supply_voltage)
netlist.set_component_value('V2', -supply_voltage)
# overriding the automatic netlist naming
run_netlist_file = "{}_{}_{}.net".format(netlist.netlist_file.stem, opamp, supply_voltage)
run_netlist_file = "{}_{}_{}.net".format(netlist.circuit_file.stem, opamp, supply_voltage)
if use_run_now:
runner.run_now(netlist, run_filename=run_netlist_file)
else:
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