5710

5710 project

This is the readme. Not very helpful but it is a central repsository for our VLSI library.

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
.abstract/verify		.abstract/verify
.cadence/dfII		.cadence/dfII
Controller		Controller
ControllerV2		ControllerV2
ERC		ERC
ExperimentalCells		ExperimentalCells
LVS		LVS
LVSf		LVSf
Lib6710_08		Lib6710_08
TestCells		TestCells
TestCharacterize		TestCharacterize
elc		elc
elc0		elc0
elc_lab6		elc_lab6
elc_lab7		elc_lab7
elc_turnin		elc_turnin
experimentalelc		experimentalelc
gridTemplate		gridTemplate
libfiles		libfiles
lvs		lvs
reports/lab7		reports/lab7
run		run
simulation		simulation
soc		soc
synth		synth
verilog_tests		verilog_tests
.cdsinit		.cdsinit
.gitignore		.gitignore
FixPerms.sh		FixPerms.sh
Lib6710_08.db		Lib6710_08.db
Lib6710_08.lef		Lib6710_08.lef
Lib6710_08.lef~		Lib6710_08.lef~
Lib6710_08.lib		Lib6710_08.lib
Lib6710_08.v		Lib6710_08.v
README.md		README.md
RemoveLocks.sh		RemoveLocks.sh
abstract.log.1		abstract.log.1
abstract.record		abstract.record
abstract.record.1		abstract.record.1
cds.lib		cds.lib
cdsLibMgr.il		cdsLibMgr.il
dfIIabstract.log1		dfIIabstract.log1
encounter.cmd		encounter.cmd
encounter.cmd1		encounter.cmd1
encounter.log1		encounter.log1
git		git
lefout.list		lefout.list
libManager.log.1		libManager.log.1
libManager.log.2		libManager.log.2
libManager.log.3		libManager.log.3

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