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CMSIS-Core(M) added Integrity Signature + FNC_RETURN (completes reque…
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…st under issue ARM-software#340)
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@ReinhardKeil
ReinhardKeil committed May 30, 2018
1 parent 94cdfe9 commit 711825c
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Showing 4 changed files with 51 additions and 3 deletions.
14 changes: 13 additions & 1 deletion CMSIS/Core/Include/core_armv8mbl.h
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Expand Up @@ -2,7 +2,7 @@
* @file core_armv8mbl.h
* @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 28. May 2018
* @date 30. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -1269,6 +1269,11 @@ typedef struct
#define NVIC_USER_IRQ_OFFSET 16


/* Special LR values for Secure/Non-Secure call handling and exception handling */

/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
Expand All @@ -1278,6 +1283,13 @@ typedef struct
#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif


/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
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14 changes: 13 additions & 1 deletion CMSIS/Core/Include/core_armv8mml.h
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Expand Up @@ -2,7 +2,7 @@
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 28. May 2018
* @date 30. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -2139,6 +2139,11 @@ typedef struct
#define NVIC_USER_IRQ_OFFSET 16


/* Special LR values for Secure/Non-Secure call handling and exception handling */

/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
Expand All @@ -2148,6 +2153,13 @@ typedef struct
#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif


/**
\brief Set Priority Grouping
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14 changes: 13 additions & 1 deletion CMSIS/Core/Include/core_cm23.h
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Expand Up @@ -2,7 +2,7 @@
* @file core_cm23.h
* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 28. May 2018
* @date 30. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -1272,6 +1272,11 @@ typedef struct
#define NVIC_USER_IRQ_OFFSET 16


/* Special LR values for Secure/Non-Secure call handling and exception handling */

/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
Expand All @@ -1281,7 +1286,14 @@ typedef struct
#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif


/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
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12 changes: 12 additions & 0 deletions CMSIS/Core/Include/core_cm33.h
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Expand Up @@ -2157,6 +2157,11 @@ typedef struct
#define NVIC_USER_IRQ_OFFSET 16


/* Special LR values for Secure/Non-Secure call handling and exception handling */

/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
Expand All @@ -2166,6 +2171,13 @@ typedef struct
#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATUR (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif


/**
\brief Set Priority Grouping
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