/
dmix_t.v
217 lines (197 loc) · 4.27 KB
/
dmix_t.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
`timescale 1ns / 1ps
module dmix_t;
// ins
reg rst;
reg signal;
parameter TclkSPDIF = 40; // 24.576MHz == 192Khz * 32 bit * 2 (biphase)
dmix_top uut(.rst(rst), .spdif_i(signal));
task recv_rawbit;
input wire b;
begin
signal = b;
#(TclkSPDIF);//*6);
end
endtask
task recv_B;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_M;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
end
end
endtask
task recv_W;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_bmcbit;
input wire b;
begin
if(signal) begin
if(b) begin
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(0);
recv_rawbit(0);
end
end else begin
if(b) begin
recv_rawbit(1);
recv_rawbit(0);
end else begin
recv_rawbit(1);
recv_rawbit(1);
end
end
end
endtask
task recv_bmcbyte;
input wire [7:0] byte;
begin
recv_bmcbit(byte[0]);
recv_bmcbit(byte[1]);
recv_bmcbit(byte[2]);
recv_bmcbit(byte[3]);
recv_bmcbit(byte[4]);
recv_bmcbit(byte[5]);
recv_bmcbit(byte[6]);
recv_bmcbit(byte[7]);
end
endtask
task recv_bmcctl;
begin
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
end
endtask
task recv_subframe;
input wire [23:0] data;
begin
recv_bmcbyte(data[7:0]);
recv_bmcbyte(data[15:8]);
recv_bmcbyte(data[23:16]);
recv_bmcctl();
end
endtask
// `define USE_CAPTURE
reg [22:0] counter;
initial begin
$dumpfile("dmix_t.lxt");
$dumpvars(0, uut);
rst = 1'b0;
signal = 0;
counter <= 0;
#(10);
rst = 1'b1;
#(40);
rst = 1'b0;
#(50);
end
`ifndef USE_CAPTURE
always begin
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
$finish(2);
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
if (counter > 512)
$finish(2);
end
`else
reg [31:0] capture [262143:0];
integer capture_iter;
initial $readmemh("spdif_capture3", capture);
initial capture_iter = 0;
always begin
signal = capture[capture_iter][2];
capture_iter = capture_iter + 1;
if (capture_iter > 262143)
$finish(2);
#(5);
end
`endif
endmodule