Test brn and brz

obiwanus · Jul 16, 2017 · d1aa7f7 · d1aa7f7
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diff --git a/processor/tests/instructions/brn/brn.mips b/processor/tests/instructions/brn/brn.mips
@@ -0,0 +1,46 @@
+    j start_program  # so the address of loop is always fixed
+
+# ===============================================
+# The loop increments counter by 2 each cycle
+# a0 = initial counter
+# a1 = number of cycles
+loop1:
+    addi    $t0, $zero, 0       # internal counter
+loop1_int:
+    addi    $a0, $a0, 2         # increment counter
+    addi    $t0, $t0, 1         # count
+    bne     $t0, $a1, loop1_int
+    j end_loop1
+
+# address should be 24
+loop2:
+    addi    $t0, $zero, 0       # internal counter
+loop2_int:
+    addi    $a0, $a0, 2         # increment counter
+    addi    $t0, $t0, 1         # count
+    bne     $t0, $a1, loop2_int
+    j end_loop2
+
+# ===============================================
+start_program:
+
+    # Store the address of loop in register
+    # so we can then branch to it
+    addi    $s0, $zero, 4   # 4 is the address of loop1
+
+    addi    $a0, $zero, 0   # counter
+    addi    $a1, $zero, 2   # number of cycles
+
+    addi    $t0, $zero, 1   # not zero
+    brn     $s0             # should branch
+end_loop1:
+
+    addi    $s0, $zero, 24  # 24 is the address of loop2
+    addi    $a0, $zero, 0   # counter
+    addi    $a1, $zero, 2   # number of cycles
+
+    addi    $t0, $zero, 0   # zero
+    brn     $s0             # should not branch
+end_loop2:
+
+
diff --git a/processor/tests/instructions/brn/brn.v b/processor/tests/instructions/brn/brn.v
@@ -0,0 +1,34 @@
+`include "_const.v"
+`include "_assert.v"
+
+module test_brn;
+    reg error = 0;
+    processor CPU();
+
+    initial begin
+        $readmemb("tests/instructions/brn/brn_imem.dat", CPU.IFU.imemory.storage.bytes);
+
+        repeat(6) @(posedge CPU.clk);
+
+        `assertEq(CPU.registers.registers[`REG_S0], 32'd4)
+        `assertEq(CPU.registers.registers[`REG_A0], 32'd0)
+        `assertEq(CPU.registers.registers[`REG_A1], 32'd2)
+        `assertEq(CPU.registers.registers[`REG_T0], 32'd1)
+
+        repeat(8) @(posedge CPU.clk);
+
+        `assertEq(CPU.registers.registers[`REG_A0], 32'd4)
+        `assertEq(CPU.registers.registers[`REG_A1], 32'd2)
+
+        repeat(9) @(posedge CPU.clk);
+
+        // Should be unchanged since the branch was not taken
+        `assertEq(CPU.registers.registers[`REG_S0], 32'd24)
+        `assertEq(CPU.registers.registers[`REG_A0], 32'd0)
+        `assertEq(CPU.registers.registers[`REG_A1], 32'd2)
+
+
+        `printResults
+    end
+
+endmodule
diff --git a/processor/tests/instructions/brn/brn_imem.dat b/processor/tests/instructions/brn/brn_imem.dat
@@ -0,0 +1,84 @@
+00001011
+00000000
+00000000
+00001000
+00000000
+00000000
+00001000
+00100000
+00000010
+00000000
+10000100
+00100000
+00000001
+00000000
+00001000
+00100001
+11111101
+11111111
+00000101
+00010101
+00010000
+00000000
+00000000
+00001000
+00000000
+00000000
+00001000
+00100000
+00000010
+00000000
+10000100
+00100000
+00000001
+00000000
+00001000
+00100001
+11111101
+11111111
+00000101
+00010101
+00010101
+00000000
+00000000
+00001000
+00000100
+00000000
+00010000
+00100000
+00000000
+00000000
+00000100
+00100000
+00000010
+00000000
+00000101
+00100000
+00000001
+00000000
+00001000
+00100000
+00010101
+00000000
+00000000
+00000010
+00011000
+00000000
+00010000
+00100000
+00000000
+00000000
+00000100
+00100000
+00000010
+00000000
+00000101
+00100000
+00000000
+00000000
+00001000
+00100000
+00010101
+00000000
+00000000
+00000010
diff --git a/processor/tests/instructions/brz/brz.mips b/processor/tests/instructions/brz/brz.mips
@@ -0,0 +1,46 @@
+    j start_program  # so the address of loop is always fixed
+
+# ===============================================
+# The loop increments counter by 2 each cycle
+# a0 = initial counter
+# a1 = number of cycles
+loop1:
+    addi    $t0, $zero, 0       # internal counter
+loop1_int:
+    addi    $a0, $a0, 2         # increment counter
+    addi    $t0, $t0, 1         # count
+    bne     $t0, $a1, loop1_int
+    j end_loop1
+
+# address should be 24
+loop2:
+    addi    $t0, $zero, 0       # internal counter
+loop2_int:
+    addi    $a0, $a0, 2         # increment counter
+    addi    $t0, $t0, 1         # count
+    bne     $t0, $a1, loop2_int
+    j end_loop2
+
+# ===============================================
+start_program:
+
+    # Store the address of loop in register
+    # so we can then branch to it
+    addi    $s0, $zero, 4   # 4 is the address of loop1
+
+    addi    $a0, $zero, 0   # counter
+    addi    $a1, $zero, 2   # number of cycles
+
+    addi    $t0, $zero, 0   # zero
+    brz     $s0             # should branch
+end_loop1:
+
+    addi    $s0, $zero, 24  # 24 is the address of loop2
+    addi    $a0, $zero, 0   # counter
+    addi    $a1, $zero, 2   # number of cycles
+
+    addi    $t0, $zero, 1   # not zero
+    brz     $s0             # should not branch
+end_loop2:
+
+
diff --git a/processor/tests/instructions/brz/brz.v b/processor/tests/instructions/brz/brz.v
@@ -0,0 +1,34 @@
+`include "_const.v"
+`include "_assert.v"
+
+module test_brz;
+    reg error = 0;
+    processor CPU();
+
+    initial begin
+        $readmemb("tests/instructions/brz/brz_imem.dat", CPU.IFU.imemory.storage.bytes);
+
+        repeat(6) @(posedge CPU.clk);
+
+        `assertEq(CPU.registers.registers[`REG_S0], 32'd4)
+        `assertEq(CPU.registers.registers[`REG_A0], 32'd0)
+        `assertEq(CPU.registers.registers[`REG_A1], 32'd2)
+        `assertEq(CPU.registers.registers[`REG_T0], 32'd0)
+
+        repeat(8) @(posedge CPU.clk);
+
+        `assertEq(CPU.registers.registers[`REG_A0], 32'd4)
+        `assertEq(CPU.registers.registers[`REG_A1], 32'd2)
+
+        repeat(9) @(posedge CPU.clk);
+
+        // Should be unchanged since the branch was not taken
+        `assertEq(CPU.registers.registers[`REG_S0], 32'd24)
+        `assertEq(CPU.registers.registers[`REG_A0], 32'd0)
+        `assertEq(CPU.registers.registers[`REG_A1], 32'd2)
+
+
+        `printResults
+    end
+
+endmodule
diff --git a/processor/tests/instructions/brz/brz_imem.dat b/processor/tests/instructions/brz/brz_imem.dat
@@ -0,0 +1,84 @@
+00001011
+00000000
+00000000
+00001000
+00000000
+00000000
+00001000
+00100000
+00000010
+00000000
+10000100
+00100000
+00000001
+00000000
+00001000
+00100001
+11111101
+11111111
+00000101
+00010101
+00010000
+00000000
+00000000
+00001000
+00000000
+00000000
+00001000
+00100000
+00000010
+00000000
+10000100
+00100000
+00000001
+00000000
+00001000
+00100001
+11111101
+11111111
+00000101
+00010101
+00010101
+00000000
+00000000
+00001000
+00000100
+00000000
+00010000
+00100000
+00000000
+00000000
+00000100
+00100000
+00000010
+00000000
+00000101
+00100000
+00000000
+00000000
+00001000
+00100000
+00010100
+00000000
+00000000
+00000010
+00011000
+00000000
+00010000
+00100000
+00000000
+00000000
+00000100
+00100000
+00000010
+00000000
+00000101
+00100000
+00000001
+00000000
+00001000
+00100000
+00010100
+00000000
+00000000
+00000010
diff --git a/processor/tests/testbench.v b/processor/tests/testbench.v
@@ -42,6 +42,8 @@ module testbench;
     // test_balmn balmn();
     // test_balmz balmz();
     // test_balrn balrn();
-    test_balrz balrz();
+    // test_balrz balrz();
+    // test_brn brn();
+    test_brz brz();
 
 endmodule