Make the scheduling pass aware of the memory model

[kayceesrk]

This is a placeholder issue in order to track the interaction of the scheduling pass and the memory model

Yes, we should fix the scheduling pass. From a quick look, it suffices to classify atomic loads like store instructions, thus preventing any reordering with other instructions that access memory. (Instructions classified as loads can be reordered with other instructions classified as loads, but not with stores.)

from #11712 (comment).

Either we disable the scheduling pass completely on OCaml 5 or we make the scheduling pass aware of the reordering allowed by the OCaml memory model.

The scheduling pass is currently disabled for x86_64 and Arm64, and #11712 disables the scheduling pass for s390x.

What about RISC-V? @nojb.

[nojb]

What about RISC-V? @nojb.

You have probably already noticed, but scheduling is also disabled in RISC-V.

[kayceesrk]

Thanks for the confirmation @nojb.