core: Define XPU triggering capability #7142
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Many HPC and AI applications use GPUs or other accelerator devices to perform computation work. FI_HMEM support allows a NIC provider to send and receive data stored on a GPU. However, the data transfer itself must still be initiated by the host CPU. This introduces delays from the time the data is ready to be transfered until the network transfer is initiated. Once the GPU is done processing the data, it must signal the CPU that the processing is complete, and then the CPU can request the network transfer. This patch introduces a new type of triggered operation, called an XPU trigger. An XPU trigger works as follows: 1. An endpoint is created with XPU triggering support. By default, all data transfers posted to the endpoint follow the XPU triggering model. 2. The host CPU makes a data transfer call (e.g. fi_write) with the FI_TRIGGER flag set. The triggering event is FI_TRIGGER_XPU. 3. A provider responds to the data transfer call by queuing the transfer, but will not initiate the transfer until a provider specified signal is set. The signal may be signaled by a device, such as a GPU or FPGA, referred to as an XPU. 4. Once an XPU writes the signal, the provider will initiate the data transfer. Details and restrictions are defined as part of the man page updates. Signed-off-by: Sean Hefty <sean.hefty@intel.com>
shefty
commented
Oct 14, 2021
| struct fi_trigger_var { | ||
| enum fi_datatype datatype; | ||
| int count; | ||
| void *addr; |
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Do we need to know what type of memory is backing this address? E.g. host memory vs NIC?
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Do providers have to provide fi_mem_write/fi_mem_read functions? To hide barrier/flush details.
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No - the writes may occur from a GPU kernel.
shefty
commented
Oct 14, 2021
| be initiated for some reason, such as an error occurring before the | ||
| transfer can start, the triggered operation should | ||
| be canceled to release any allocated resources. If multiple variables are | ||
| specified, they must be updated in order. |
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Should note that the caller must serialize writing triggers that correspond to different data transfers. All variables belonging to a single trigger must be written together and in order.
shefty
commented
Oct 14, 2021
| structures after returning from the data transfer call. | ||
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| In order to support multiple provider implementations, users should trigger | ||
| data transfer operations in the same order that they are queued and should |
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Could provide as query output whether triggers may be processed out of order by the provider.
shefty
commented
Oct 19, 2021
| @@ -166,6 +166,7 @@ typedef struct fid *fid_t; | |||
| #define FI_COMMIT_COMPLETE (1ULL << 30) | |||
| #define FI_MATCH_COMPLETE (1ULL << 31) | |||
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| #define FI_XPU (1ULL << 45) | |||
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Should this be more precise? E.g. FI_XPU_TRIGGER
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Many HPC and AI applications use GPUs or other accelerator devices
to perform computation work. FI_HMEM support allows a NIC
provider to send and receive data stored on a GPU. However,
the data transfer itself must still be initiated by the host
CPU. This introduces delays from the time the data is ready to
be transfered until the network transfer is initiated. Once
the GPU is done processing the data, it must signal the CPU
that the processing is complete, and then the CPU can request
the network transfer.
This patch introduces a new type of triggered operation, called
an XPU trigger. An XPU trigger works as follows:
An endpoint is created with XPU triggering support. By
default, all data transfers posted to the endpoint follow
the XPU triggering model.
The host CPU makes a data transfer call (e.g. fi_write)
with the FI_TRIGGER flag set. The triggering event is
FI_TRIGGER_XPU.
A provider responds to the data transfer call by queuing
the transfer, but will not initiate the transfer until a
provider specified signal is set. The signal may be signaled
by a device, such as a GPU or FPGA, referred to as an XPU.
Once an XPU writes the signal, the provider will initiate
the data transfer.
Details and restrictions are defined as part of the man
page updates.
Signed-off-by: Sean Hefty sean.hefty@intel.com