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  1. Package manager and build abstraction tool for FPGA/ASIC development

    Python 625 135

  2. SERV - The SErial RISC-V CPU

    Verilog 376 64

  3. An abstraction library for interfacing EDA tools

    Python 282 78

  4. FuseSoC standard core library

    42 15

  5. FuseSoC-based SoC for SweRV EH1

    Verilog 96 27

  6. A collection of core generators to use with FuseSoC

    Python 4 6

380 contributions in the last year

Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr Mon Wed Fri

Contribution activity

April 2021

Created 2 repositories

Created a pull request in olofk/fusesoc that received 2 comments

Add errors key for targets to report error conditions

This adds a new key to targets named 'errors' and a get_errors CAPI function. Any item in the errors list that evaluates to a non-empty string will…

+53 −0 2 comments
Opened 5 other pull requests in 4 repositories
olofk/fusesoc
1 open 1 merged
efabless/openlane
1 open
asicbitch/chip_integration_test
1 merged
olofk/edalize
1 closed

Created an issue in chipsalliance/Cores-SweRV-EL2 that received 1 comment

Debug support

I'm adding support for SweRV EL2 in SweRVolf. It seems to run fine except for the debug interface. I can read and write RAM but after trying to acc…

1 comment

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