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# Copyright edalize contributors | ||
# Licensed under the 2-Clause BSD License, see LICENSE for details. | ||
# SPDX-License-Identifier: BSD-2-Clause | ||
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import os | ||
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from edalize.tools.edatool import Edatool | ||
from edalize.utils import EdaCommands | ||
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MAKEFILE_TEMPLATE = """ | ||
all: $(VPI_MODULES) $(TARGET) | ||
run: $(VPI_MODULES) $(TARGET) | ||
vvp -n -M. -l icarus.log $(patsubst %.vpi,-m%,$(VPI_MODULES)) $(TARGET) -fst $(EXTRA_OPTIONS) | ||
clean: | ||
$(RM) $(VPI_MODULES) $(TARGET) | ||
""" | ||
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VPI_MAKE_SECTION = """ | ||
{name}_LIBS := {libs} | ||
{name}_INCS := {incs} | ||
{name}_SRCS := {srcs} | ||
{name}.vpi: $({name}_SRCS) | ||
iverilog-vpi --name={name} $({name}_LIBS) $({name}_INCS) $? | ||
clean_{name}: | ||
$(RM) {name}.vpi | ||
""" | ||
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class Icarus(Edatool): | ||
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description = "Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format" | ||
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TOOL_OPTIONS = { | ||
"timescale": { | ||
"type": "str", | ||
"desc": "Default timescale", | ||
}, | ||
"iverilog_options": { | ||
"type": "str", | ||
"desc": "Additional options for iverilog", | ||
}, | ||
} | ||
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def configure(self, edam): | ||
super().configure(edam) | ||
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incdirs = [] | ||
vlog_files = [] | ||
depfiles = [] | ||
unused_files = [] | ||
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with open(os.path.join(self.work_root, self.name + ".scr"), "w") as scr_file: | ||
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for key, value in self.vlogdefine.items(): | ||
scr_file.write( | ||
"+define+{}={}\n".format(key, self._param_value_str(value, "")) | ||
) | ||
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for key, value in self.vlogparam.items(): | ||
scr_file.write( | ||
"+parameter+{}.{}={}\n".format( | ||
self.toplevel, key, self._param_value_str(value, '"') | ||
) | ||
) | ||
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for id in incdirs: | ||
scr_file.write("+incdir+" + id + "\n") | ||
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timescale = self.tool_options.get("timescale") | ||
if timescale: | ||
with open(os.path.join(self.work_root, "timescale.v"), "w") as tsfile: | ||
tsfile.write("`timescale {}\n".format(timescale)) | ||
scr_file.write("timescale.v\n") | ||
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for f in self.files: | ||
file_type = f.get("file_type", "") | ||
depfile = True | ||
if file_type.startswith("systemVerilogSource") or file_type.startswith( | ||
"verilogSource" | ||
): | ||
if not self._add_include_dir(f, incdirs): | ||
vlog_files.append(f["name"]) | ||
else: | ||
unused_files.append(f) | ||
depfile = False | ||
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if depfile: | ||
depfiles.append(f["name"]) | ||
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for include_dir in incdirs: | ||
scr_file.write(f"+incdir+{include_dir}\n") | ||
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for vlog_file in vlog_files: | ||
scr_file.write(f"{vlog_file}\n") | ||
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self.edam = edam.copy() | ||
self.edam["files"] = unused_files | ||
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commands = EdaCommands() | ||
commands.add( | ||
[ | ||
"iverilog", | ||
f"-s{self.toplevel}", | ||
"-c", | ||
f"{self.name}.scr", | ||
"-o", | ||
self.name, | ||
] | ||
+ self.tool_options.get("iverilog_options", []), | ||
[self.name], | ||
depfiles + [f"{self.name}.scr"], | ||
) | ||
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# How should the run target be handled? | ||
# Add VPI support | ||
commands.add( | ||
["vvp", "-n", "-M.", self.name, "-fst", "$(EXTRA_OPTIONS)"], | ||
["run"], | ||
[self.name], | ||
) | ||
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self.default_target = self.name | ||
self.commands = commands.commands | ||
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def run(self, args): | ||
args = ["run"] | ||
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# Set plusargs | ||
if self.plusarg: | ||
plusargs = [] | ||
for key, value in self.plusarg.items(): | ||
plusargs += ["+{}={}".format(key, self._param_value_str(value))] | ||
args.append("EXTRA_OPTIONS=" + " ".join(plusargs)) | ||
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return ("make", args, self.work_root) |