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DC vlogdefine params (#2)
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* added vlogdefine support for dc.

* Added missing return.

* Generate string and not list of string characters.

* merge defines in one otherwise overwritten by last define.

* merge defines in one otherwise overwritten by last define.

* Code cleaning.
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benoitdenkinger authored and olofk committed Apr 25, 2023
1 parent 0213110 commit c3b3eed
Showing 1 changed file with 17 additions and 4 deletions.
21 changes: 17 additions & 4 deletions edalize/design_compiler.py
Original file line number Diff line number Diff line change
Expand Up @@ -111,9 +111,9 @@ def make_list(opt):

def src_file_filter(self, f):
file_types = {
'verilogSource' : 'analyze -format verilog -work work',
'systemVerilogSource' : 'analyze -format sverilog -work work',
'vhdlSource' : 'analyze -format vhdl -work work',
'verilogSource' : 'analyze -format verilog',
'systemVerilogSource' : 'analyze -format sverilog',
'vhdlSource' : 'analyze -format vhdl',
# 'xci' : 'read_ip',
# 'xdc' : 'read_xdc',
# 'tclSource' : 'source',
Expand All @@ -122,7 +122,20 @@ def src_file_filter(self, f):
}
_file_type = f.file_type.split('-')[0]
if _file_type in file_types:
return file_types[_file_type] + ' ' + f.name
cmd = ""
cmd += file_types[_file_type] + ' '

cmd_define = ""
if self.vlogdefine.items() != {}:
cmd_define = "-define {"
for k, v in self.vlogdefine.items():
# SKip reddefinition of SYNTHESIS which is a reserved macro in IEEE Verilog synthesizable subset
if k != 'SYNTHESIS':
cmd_define += " {}={}".format(k, self._param_value_str(v))
cmd_define += " }"

cmd += cmd_define + ' ' + '-work work ' + f.name
return cmd

if _file_type == 'user':
return ''
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