verilator: Add verilator config files before any verilog files

olofk · Jul 23, 2019 · e7fde24 · e7fde24
1 parent 0497185
commit e7fde24
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Showing 4 changed files with 10 additions and 5 deletions.
diff --git a/edalize/verilator.py b/edalize/verilator.py
@@ -108,17 +108,22 @@ def _write_config_files(self):
             for include_dir in incdirs:
                 f.write("+incdir+" + include_dir + '\n')
                 f.write("-CFLAGS -I{}\n".format(include_dir))
+            vlt_files = []
+            vlog_files = []
             opt_c_files = []
             for src_file in src_files:
                 if src_file.file_type.startswith("systemVerilogSource") or src_file.file_type.startswith("verilogSource"):
-                    f.write(src_file.name + '\n')
+                    vlog_files.append(src_file.name)
                 elif src_file.file_type in ['cppSource', 'systemCSource', 'cSource']:
                     opt_c_files.append(src_file.name)
                 elif src_file.file_type == 'vlt':
-                    f.write(src_file.name + '\n')
+                    vlt_files.append(src_file.name)
                 elif src_file.file_type == 'user':
                     pass
 
+            if vlt_files:
+                f.write('\n'.join(vlt_files) + '\n')
+            f.write('\n'.join(vlog_files) + '\n')
             f.write('--top-module {}\n'.format(self.toplevel))
             f.write('--exe\n')
             f.write('\n'.join(opt_c_files))

diff --git a/tests/test_verilator/cc/mor1kx-generic_0.vc b/tests/test_verilator/cc/mor1kx-generic_0.vc
@@ -17,6 +17,7 @@
 -CFLAGS -I../../../cores/mor1kx-generic/rtl/verilog
 +incdir+../../../cores/mor1kx-generic/bench/verilog/include
 -CFLAGS -I../../../cores/mor1kx-generic/bench/verilog/include
+../../../cores/misc/waiver.vlt
 ../../../cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
 ../../../cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
 ../../../cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v
@@ -31,7 +32,6 @@
 ../../../cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/syncreg.v
 ../../../cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
 ../../../cores/misc/sv_file.sv
-../../../cores/misc/waiver.vlt
 ../../../cores/misc/vlog_file.v
 ../../../cache/jtag_tap_1.13/tap/rtl/verilog/tap_top.v
 ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_branch_prediction.v

diff --git a/tests/test_verilator/lint-only/mor1kx-generic_0.vc b/tests/test_verilator/lint-only/mor1kx-generic_0.vc
@@ -4,8 +4,8 @@
 -CFLAGS -I../../../cores/verilator_tb_utils
 +incdir+../../../cores/mor1kx-generic/bench/verilog/include
 -CFLAGS -I../../../cores/mor1kx-generic/bench/verilog/include
-../../../cores/mor1kx-generic/rtl/verilog/wb_intercon.v
 ../../../cores/mor1kx-generic/bench/verilator/waiver.vlt
+../../../cores/mor1kx-generic/rtl/verilog/wb_intercon.v
 --top-module orpsoc_top
 --exe
 ../../../cores/verilator_tb_utils/verilator_tb_utils.cpp

diff --git a/tests/test_verilator/sc/mor1kx-generic_0.vc b/tests/test_verilator/sc/mor1kx-generic_0.vc
@@ -4,8 +4,8 @@
 -CFLAGS -I../../../cores/verilator_tb_utils
 +incdir+../../../cores/mor1kx-generic/bench/verilog/include
 -CFLAGS -I../../../cores/mor1kx-generic/bench/verilog/include
-../../../cores/mor1kx-generic/rtl/verilog/wb_intercon.v
 ../../../cores/mor1kx-generic/bench/verilator/waiver.vlt
+../../../cores/mor1kx-generic/rtl/verilog/wb_intercon.v
 --top-module orpsoc_top
 --exe
 ../../../cores/verilator_tb_utils/verilator_tb_utils.cpp