Add VHDL generic support for ISE

olofk · Mar 14, 2019 · eb9a591 · eb9a591
1 parent 926cb35
commit eb9a591
Showing 1 changed file with 5 additions and 3 deletions.
diff --git a/edalize/ise.py b/edalize/ise.py
@@ -10,7 +10,7 @@ class Ise(Edatool):
                                  'package' : 'String',
                                  'speed'   : 'String'}}
 
-    argtypes = ['vlogdefine', 'vlogparam']
+    argtypes = ['vlogdefine', 'vlogparam', 'generic']
 
     MAKEFILE_TEMPLATE = """#Auto generated by Edalize
 include config.mk
@@ -109,9 +109,11 @@ def _write_tcl_file(self):
             s = 'project set "Verilog Macros" "{}" -process "Synthesize - XST"\n'
             tcl_file.write(s.format('|'.join([k+'='+self._param_value_str(v) for k,v in self.vlogdefine.items()])))
 
-        if self.vlogparam:
+        if self.vlogparam or self.generic:
+            genparam = self.vlogparam.copy()
+            genparam.update(self.generic)
             s = 'project set "Generics, Parameters" "{}" -process "Synthesize - XST"\n'
-            tcl_file.write(s.format('|'.join([k+'='+self._param_value_str(v, '\\"') for k,v in self.vlogparam.items()])))
+            tcl_file.write(s.format('|'.join([k+'='+self._param_value_str(v, '\\"') for k,v in genparam.items()])))
 
         (src_files, incdirs) = self._get_fileset_files()