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It would be really great if there was inbuilt support in FuseSoC / edalize for this flow. It would mean we could get more real world designs into the VtR benchmarks (and thus enable more research that is applicable to real world stuff!).
The process seems to be;
3. VQM GENERATION
To generate BLIF, a Verilog Quartus Map (VQM) file must first be produced by Quartus II.
To enable VQM generation, hidden variables must be added to Quartus settings file (.qsf) before synthesis is performed. This is shown in Listing 2 for the Stratix IV family.
Listing 2: Assignments added to the .qsf for VQM Generation
The plain-text VQM can now be converted to BLIF, using the vqm2blif tool, as shown in Listing 5. Advanced usage is described in vqm2blif’s documentation.
The generated BLIF file can now be used in academic CAD tools that read BLIF. Figure 1 shows the placement generated by VPR [2], created with the command shown in Listing 6.
Listing 6: VPR command to generate Figure 1
$ vpr ../test_arch.xml bc_small.blif --timing_analysis off
The text was updated successfully, but these errors were encountered:
Verilog to Routing supports using Quartus as a frontend for synthesis and then VtR for doing the place and route. You can find out more about this flow @ http://www.eecg.utoronto.ca/~kmurray/titan/fpl_13_demo.pdf
It would be really great if there was inbuilt support in FuseSoC / edalize for this flow. It would mean we could get more real world designs into the VtR benchmarks (and thus enable more research that is applicable to real world stuff!).
The process seems to be;
The text was updated successfully, but these errors were encountered: