Add testcases for vivado

fusesoc/build/vivado.py

@@ -85,10 +85,10 @@ def _write_project_tcl_file(self):
 
         parameters = ""
         for key, value in self.vlogparam.items():
-            parameters += "set_property generic {{{key}={value}}} [get_filesets sources_1]".format(key=key, value=value)
+            parameters += "set_property generic {{{key}={value}}} [get_filesets sources_1]\n".format(key=key, value=value)
 
         if len(self.vlogdefine.items()) > 0:
-            parameters += "set_property verilog_define \"{}\" [get_filesets sources_1]".format(" ".join(k+"="+v for k,v in self.vlogdefine.items()))
+            parameters += "set_property verilog_define \"{}\" [get_filesets sources_1]\n".format(" ".join(k+"="+v for k,v in self.vlogdefine.items()))
 
         if self.backend.top_module:
             extras += "set_property top "+self.backend.top_module+" [current_fileset]"
@@ -97,7 +97,7 @@ def _write_project_tcl_file(self):
         tcl_file.write(PROJECT_TCL_TEMPLATE.format(
             design       = self.system.sanitized_name,
             part         = self.system.backend.part,
-            bitstream    = os.path.join(self.work_root, self.system.sanitized_name+'.bit'),
+            bitstream    = self.system.sanitized_name+'.bit',
             incdirs      = ' '.join(incdirs),
             ip           = ipconfig,
             parameters   = parameters,

tests/cores/mor1kx-arty/mor1kx-arty.core

@@ -0,0 +1,10 @@
+CAPI=1
+[main]
+depend =
+ filetypes
+ mor1kx
+ paramtest
+
+[verilog]
+src_files =
+  rtl/verilog/mor1kx_arty.sv

tests/cores/mor1kx-arty/mor1kx-arty.system

@@ -0,0 +1,11 @@
+SAPI=1
+[main]
+name = mor1kx-arty
+description = "Xilinx/Digilent Arty board OpenRISC system"
+
+backend = vivado
+
+[vivado]
+part = "xc7a35tcsg324-1"
+hw_device = xc7a35t_0
+top_module = mor1kx_arty_top

tests/test_vivado.py

@@ -0,0 +1,26 @@
+import difflib
+import os
+import pytest
+
+from test_common import compare_file, get_core, get_synth, vlogdefines, vlogparams
+
+tests_dir = os.path.dirname(__file__)
+params = vlogparams + vlogdefines
+core = get_core("mor1kx-arty")
+backend = get_synth('vivado', core)
+ref_dir = os.path.join(tests_dir, __name__)
+work_root = backend.work_root
+
+def test_vivado_configure():
+
+    backend.configure(params)
+
+    tcl_file = core.name.sanitized_name + '.tcl'
+
+    assert '' == compare_file(ref_dir, work_root, tcl_file)
+
+def test_vivado_build():
+    os.environ['PATH'] = os.path.join(tests_dir, 'mock_commands')+':'+os.environ['PATH']
+    backend.build(params)
+
+    assert '' == compare_file(ref_dir, work_root, 'run.cmd')

tests/test_vivado/mor1kx-arty_0.tcl

@@ -0,0 +1,78 @@
+# Auto-generated project tcl file
+
+create_project -part "xc7a35tcsg324-1" mor1kx-arty_0
+
+set_property "simulator_language" "Mixed" [current_project]
+
+source ../../../cores/misc/tcl_file.tcl
+
+read_ip ../../../cores/misc/xci_file.xci
+upgrade_ip [get_ips]
+generate_target all [get_ips]
+
+
+read_verilog ../../../cores/misc/vlog_file.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_branch_prediction.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_bus_if_avalon.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_bus_if_wb32.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_cache_lru.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_cfgrs.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_cpu_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_cpu_espresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_cpu.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_ctrl_espresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_dcache.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_decode.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_dmmu.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_execute_alu.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_fetch_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_fetch_espresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_icache.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_immu.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_lsu_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_lsu_espresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_pic.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_rf_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_rf_espresso.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_store_buffer.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_ticktimer.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_true_dpram_sclk.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v
+read_verilog ../../../cache/mor1kx_3.1/rtl/verilog/mor1kx_wb_mux_espresso.v
+read_verilog ../../../cores/mor1kx-arty/rtl/verilog/mor1kx_arty.sv
+read_verilog -sv ../../../cores/misc/sv_file.sv
+read_vhdl ../../../cores/misc/vhdl_file.vhd
+read_vhdl -library libx ../../../cores/misc/vhdl_lib_file.vhd
+read_vhdl -vhdl2008 ../../../cores/misc/vhdl2008_file.vhd
+
+set_property generic {vlogparam_bool=true} [get_filesets sources_1]
+set_property generic {vlogparam_int=42} [get_filesets sources_1]
+set_property generic {vlogparam_str="hello"} [get_filesets sources_1]
+set_property verilog_define "vlogdefine_bool=true vlogdefine_int=42 vlogdefine_str=hello" [get_filesets sources_1]
+
+
+set_property include_dirs [list ../../../cache/mor1kx_3.1/rtl/verilog] [get_filesets sources_1]
+
+read_xdc ../../../cores/misc/xdc_file
+
+set_param project.enableVHDL2008 1
+set_property top mor1kx_arty_top [current_fileset]
+
+regexp -- {Vivado v([0-9]{4})\.[0-9]} [version] -> year
+
+create_run -name synthesis -flow "Vivado Synthesis $year" -strategy "Vivado Synthesis Defaults"
+create_run implementation -flow "Vivado Implementation $year" -strategy "Vivado Implementation Defaults" -parent_run synthesis
+
+launch_runs implementation
+wait_on_run implementation
+open_run implementation
+write_bitstream mor1kx-arty_0.bit

tests/test_vivado/run.cmd

@@ -0,0 +1 @@
+-mode batch -source /home/olof/code/fusesoc/tests/build/mor1kx-arty_0/bld-vivado/mor1kx-arty_0.tcl