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Overclock to 1.3Ghz

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1 parent 60fb759 commit fa382323fd1fafd056fbc62fcbe3b3fc19e3432d @omegamoon committed Aug 16, 2012
Showing with 38 additions and 1 deletion.
  1. +9 −1 arch/arm/mach-msm/Kconfig
  2. +29 −0 arch/arm/mach-msm/acpuclock-7201.c
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@@ -1571,13 +1571,21 @@ config MSM_CPU_FREQ_SET_MIN_MAX
config MSM_CPU_FREQ_MAX
int "Max CPU Frequency"
depends on MSM_CPU_FREQ_SET_MIN_MAX
- default 384000
+ default 1008000
config MSM_CPU_FREQ_MIN
int "Min CPU Frequency"
depends on MSM_CPU_FREQ_SET_MIN_MAX
default 245760
+config MSM7X27AA_OVERCLOCK
+ bool "Enable overclock for Huawei G300"
+ depends on MSM_CPU_FREQ_SET_MIN_MAX
+ default n
+ help
+ Enable overclock for Huawei G300. NOT tested. Make sure to enable
+ Max CPU Frequency to 1008000
+
endif # CPU_FREQ_MSM
config MSM_CPU_AVS
@@ -223,6 +223,16 @@ static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_1008[] = {
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 200000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
+ #ifdef CONFIG_MSM7X27AA_OVERCLOCK
+ { 1, 1036800, ACPU_PLL_4, 6, 0, 129600, 3, 7, 200000 },
+ { 1, 1056000, ACPU_PLL_4, 6, 0, 132000, 3, 7, 200000 },
+ { 1, 1113600, ACPU_PLL_4, 6, 0, 139200, 3, 7, 200000 },
+ { 1, 1152000, ACPU_PLL_4, 6, 0, 144000, 3, 7, 200000 },
+ { 1, 1190400, ACPU_PLL_4, 6, 0, 148800, 3, 7, 200000 },
+ { 1, 1228800, ACPU_PLL_4, 6, 0, 153600, 3, 7, 200000 },
+ { 1, 1267200, ACPU_PLL_4, 6, 0, 158400, 3, 7, 200000 },
+ { 1, 1305600, ACPU_PLL_4, 6, 0, 163200, 3, 7, 200000 },
+ #endif
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
};
@@ -492,6 +502,16 @@ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s)
/* AHB_CLK_DIV */
clk_div = (reg_clksel >> 1) & 0x03;
+
+ #ifdef CONFIG_MSM7X27AA_OVERCLOCK
+ // Perform overclocking if requested
+ if (hunt_s->a11clk_khz > 1008000) {
+ // Change the speed of PLL4
+ writel(hunt_s->a11clk_khz/19200,PLL4_L_VAL);
+ udelay(50);
+ }
+ #endif
+
/* CLK_SEL_SRC1NO */
src_sel = reg_clksel & 1;
@@ -516,6 +536,15 @@ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s)
reg_clksel ^= 1;
writel_relaxed(reg_clksel, A11S_CLK_SEL_ADDR);
+ #ifdef CONFIG_MSM7X27AA_OVERCLOCK
+ // Recover from overclocking
+ if (hunt_s->a11clk_khz<=1008000) {
+ // Restore the speed of PLL4
+ writel(PLL_1008_MHZ, PLL4_L_VAL);
+ udelay(50);
+ }
+ #endif
+
/*
* If the new clock divider is lower than the previous, then
* program the divider after switching the clock

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