GitHub - omkarkac/Synopsys-VCS-Verilog: Includes all the projects undertaken during my Masters Course at Sac State. In the course Hierarchical Design Methodology.

omkarkac / Synopsys-VCS-Verilog Public

Includes all the projects undertaken during my Masters Course at Sac State. In the course Hierarchical Design Methodology.

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Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
EEE273_Term_project_report1.pdf		EEE273_Term_project_report1.pdf
README_alu.md		README_alu.md
README_seqdt.md		README_seqdt.md
alu.v		alu.v
alu_fixture.v		alu_fixture.v
seqdt.v		seqdt.v
seqdt_fixture.v		seqdt_fixture.v