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tests/linux: add a testcase with memory side caches
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We only ever had KNL with MSC but this case doesn't use
the official HMAT-based Linux sysfs discovery.

Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
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bgoglin committed Aug 24, 2023
1 parent ac1f8db commit 3c08229
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3 changes: 3 additions & 0 deletions tests/hwloc/linux/Makefile.am
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Expand Up @@ -55,6 +55,7 @@ sysfs_tests = \
fakeheterocpunuma.test \
fakeheteromemtiers.test \
fakememinitiators-1np2c+1npp+gi.test \
memorysidecaches.test \
nvidiagpunumanodes.test \
nvidiagpunumanodes-kept.test \
offline-cpu0-node0.test
Expand Down Expand Up @@ -101,6 +102,7 @@ sysfs_tarballs = \
fakeheterocpunuma.tar.bz2 \
fakeheteromemtiers.tar.bz2 \
fakememinitiators-1np2c+1npp+gi.tar.bz2 \
memorysidecaches.tar.bz2 \
nvidiagpunumanodes.tar.bz2 \
offline-cpu0-node0.tar.bz2

Expand Down Expand Up @@ -143,6 +145,7 @@ sysfs_console_outputs = \
fakecpuid1f-64intel64-2p4d2n2c2t.console \
fakeheteromemtiers.console \
fakememinitiators-1np2c+1npp+gi.console \
memorysidecaches.console \
nvidiagpunumanodes.console \
nvidiagpunumanodes-kept.console \
offline-cpu0-node0.console
Expand Down
276 changes: 276 additions & 0 deletions tests/hwloc/linux/memorysidecaches.console
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@@ -0,0 +1,276 @@
Machine (P#0 total=1487GiB DMIProductName="PowerEdge R740" DMIProductVersion= DMIBoardVendor="Dell Inc." DMIBoardName=01YM03 DMIBoardVersion=A02 DMIChassisVendor="Dell Inc." DMIChassisType=23 DMIChassisVersion= DMIChassisAssetTag= DMIBIOSVendor="Dell Inc." DMIBIOSVersion=2.2.11 DMIBIOSDate=06/13/2019 DMISysVendor="Dell Inc.")
Package L#0 (P#0 total=743GiB CPUVendor=GenuineIntel CPUFamilyNumber=6 CPUModelNumber=85 CPUModel="Intel(R) Xeon(R) Gold 6230 CPU @ 2.10GHz" CPUStepping=7)
L3Cache L#0 (P#0 total=743GiB size=28MiB linesize=64 ways=11)
Group0 L#0 (total=370GiB)
MemCache L#0 (total=370GiB size=96GiB linesize=64 ways=1)
NUMANode L#0 (P#0 local=370GiB total=370GiB)
L2Cache L#0 (P#0 size=1024KiB linesize=64 ways=16)
L1dCache L#0 (P#0 size=32KiB linesize=64 ways=8)
L1iCache L#0 (P#0 size=32KiB linesize=64 ways=8)
Core L#0 (P#0)
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L2Cache L#1 (P#1 size=1024KiB linesize=64 ways=16)
L1dCache L#1 (P#1 size=32KiB linesize=64 ways=8)
L1iCache L#1 (P#1 size=32KiB linesize=64 ways=8)
Core L#1 (P#1)
PU L#2 (P#4)
PU L#3 (P#44)
L2Cache L#2 (P#2 size=1024KiB linesize=64 ways=16)
L1dCache L#2 (P#2 size=32KiB linesize=64 ways=8)
L1iCache L#2 (P#2 size=32KiB linesize=64 ways=8)
Core L#2 (P#2)
PU L#4 (P#8)
PU L#5 (P#48)
L2Cache L#3 (P#8 size=1024KiB linesize=64 ways=16)
L1dCache L#3 (P#8 size=32KiB linesize=64 ways=8)
L1iCache L#3 (P#8 size=32KiB linesize=64 ways=8)
Core L#3 (P#8)
PU L#6 (P#12)
PU L#7 (P#52)
L2Cache L#4 (P#9 size=1024KiB linesize=64 ways=16)
L1dCache L#4 (P#9 size=32KiB linesize=64 ways=8)
L1iCache L#4 (P#9 size=32KiB linesize=64 ways=8)
Core L#4 (P#9)
PU L#8 (P#16)
PU L#9 (P#56)
L2Cache L#5 (P#16 size=1024KiB linesize=64 ways=16)
L1dCache L#5 (P#16 size=32KiB linesize=64 ways=8)
L1iCache L#5 (P#16 size=32KiB linesize=64 ways=8)
Core L#5 (P#16)
PU L#10 (P#20)
PU L#11 (P#60)
L2Cache L#6 (P#17 size=1024KiB linesize=64 ways=16)
L1dCache L#6 (P#17 size=32KiB linesize=64 ways=8)
L1iCache L#6 (P#17 size=32KiB linesize=64 ways=8)
Core L#6 (P#17)
PU L#12 (P#24)
PU L#13 (P#64)
L2Cache L#7 (P#18 size=1024KiB linesize=64 ways=16)
L1dCache L#7 (P#18 size=32KiB linesize=64 ways=8)
L1iCache L#7 (P#18 size=32KiB linesize=64 ways=8)
Core L#7 (P#18)
PU L#14 (P#28)
PU L#15 (P#68)
L2Cache L#8 (P#24 size=1024KiB linesize=64 ways=16)
L1dCache L#8 (P#24 size=32KiB linesize=64 ways=8)
L1iCache L#8 (P#24 size=32KiB linesize=64 ways=8)
Core L#8 (P#24)
PU L#16 (P#32)
PU L#17 (P#72)
L2Cache L#9 (P#25 size=1024KiB linesize=64 ways=16)
L1dCache L#9 (P#25 size=32KiB linesize=64 ways=8)
L1iCache L#9 (P#25 size=32KiB linesize=64 ways=8)
Core L#9 (P#25)
PU L#18 (P#36)
PU L#19 (P#76)
Group0 L#1 (total=372GiB)
MemCache L#1 (total=372GiB size=96GiB linesize=64 ways=1)
NUMANode L#1 (P#2 local=372GiB total=372GiB)
L2Cache L#10 (P#4 size=1024KiB linesize=64 ways=16)
L1dCache L#10 (P#4 size=32KiB linesize=64 ways=8)
L1iCache L#10 (P#4 size=32KiB linesize=64 ways=8)
Core L#10 (P#4)
PU L#20 (P#2)
PU L#21 (P#42)
L2Cache L#11 (P#3 size=1024KiB linesize=64 ways=16)
L1dCache L#11 (P#3 size=32KiB linesize=64 ways=8)
L1iCache L#11 (P#3 size=32KiB linesize=64 ways=8)
Core L#11 (P#3)
PU L#22 (P#6)
PU L#23 (P#46)
L2Cache L#12 (P#12 size=1024KiB linesize=64 ways=16)
L1dCache L#12 (P#12 size=32KiB linesize=64 ways=8)
L1iCache L#12 (P#12 size=32KiB linesize=64 ways=8)
Core L#12 (P#12)
PU L#24 (P#10)
PU L#25 (P#50)
L2Cache L#13 (P#11 size=1024KiB linesize=64 ways=16)
L1dCache L#13 (P#11 size=32KiB linesize=64 ways=8)
L1iCache L#13 (P#11 size=32KiB linesize=64 ways=8)
Core L#13 (P#11)
PU L#26 (P#14)
PU L#27 (P#54)
L2Cache L#14 (P#10 size=1024KiB linesize=64 ways=16)
L1dCache L#14 (P#10 size=32KiB linesize=64 ways=8)
L1iCache L#14 (P#10 size=32KiB linesize=64 ways=8)
Core L#14 (P#10)
PU L#28 (P#18)
PU L#29 (P#58)
L2Cache L#15 (P#20 size=1024KiB linesize=64 ways=16)
L1dCache L#15 (P#20 size=32KiB linesize=64 ways=8)
L1iCache L#15 (P#20 size=32KiB linesize=64 ways=8)
Core L#15 (P#20)
PU L#30 (P#22)
PU L#31 (P#62)
L2Cache L#16 (P#19 size=1024KiB linesize=64 ways=16)
L1dCache L#16 (P#19 size=32KiB linesize=64 ways=8)
L1iCache L#16 (P#19 size=32KiB linesize=64 ways=8)
Core L#16 (P#19)
PU L#32 (P#26)
PU L#33 (P#66)
L2Cache L#17 (P#28 size=1024KiB linesize=64 ways=16)
L1dCache L#17 (P#28 size=32KiB linesize=64 ways=8)
L1iCache L#17 (P#28 size=32KiB linesize=64 ways=8)
Core L#17 (P#28)
PU L#34 (P#30)
PU L#35 (P#70)
L2Cache L#18 (P#27 size=1024KiB linesize=64 ways=16)
L1dCache L#18 (P#27 size=32KiB linesize=64 ways=8)
L1iCache L#18 (P#27 size=32KiB linesize=64 ways=8)
Core L#18 (P#27)
PU L#36 (P#34)
PU L#37 (P#74)
L2Cache L#19 (P#26 size=1024KiB linesize=64 ways=16)
L1dCache L#19 (P#26 size=32KiB linesize=64 ways=8)
L1iCache L#19 (P#26 size=32KiB linesize=64 ways=8)
Core L#19 (P#26)
PU L#38 (P#38)
PU L#39 (P#78)
Package L#1 (P#1 total=744GiB CPUVendor=GenuineIntel CPUFamilyNumber=6 CPUModelNumber=85 CPUModel="Intel(R) Xeon(R) Gold 6230 CPU @ 2.10GHz" CPUStepping=7)
L3Cache L#1 (P#1 total=744GiB size=28MiB linesize=64 ways=11)
Group0 L#2 (total=372GiB)
MemCache L#2 (total=372GiB size=96GiB linesize=64 ways=1)
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L2Cache L#20 (P#32 size=1024KiB linesize=64 ways=16)
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L1iCache L#20 (P#32 size=32KiB linesize=64 ways=8)
Core L#20 (P#0)
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L2Cache L#21 (P#33 size=1024KiB linesize=64 ways=16)
L1dCache L#21 (P#33 size=32KiB linesize=64 ways=8)
L1iCache L#21 (P#33 size=32KiB linesize=64 ways=8)
Core L#21 (P#1)
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PU L#43 (P#45)
L2Cache L#22 (P#34 size=1024KiB linesize=64 ways=16)
L1dCache L#22 (P#34 size=32KiB linesize=64 ways=8)
L1iCache L#22 (P#34 size=32KiB linesize=64 ways=8)
Core L#22 (P#2)
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L1dCache L#23 (P#40 size=32KiB linesize=64 ways=8)
L1iCache L#23 (P#40 size=32KiB linesize=64 ways=8)
Core L#23 (P#8)
PU L#46 (P#13)
PU L#47 (P#53)
L2Cache L#24 (P#41 size=1024KiB linesize=64 ways=16)
L1dCache L#24 (P#41 size=32KiB linesize=64 ways=8)
L1iCache L#24 (P#41 size=32KiB linesize=64 ways=8)
Core L#24 (P#9)
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L1iCache L#25 (P#48 size=32KiB linesize=64 ways=8)
Core L#25 (P#16)
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L1iCache L#26 (P#49 size=32KiB linesize=64 ways=8)
Core L#26 (P#17)
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L1iCache L#27 (P#50 size=32KiB linesize=64 ways=8)
Core L#27 (P#18)
PU L#54 (P#29)
PU L#55 (P#69)
L2Cache L#28 (P#56 size=1024KiB linesize=64 ways=16)
L1dCache L#28 (P#56 size=32KiB linesize=64 ways=8)
L1iCache L#28 (P#56 size=32KiB linesize=64 ways=8)
Core L#28 (P#24)
PU L#56 (P#33)
PU L#57 (P#73)
L2Cache L#29 (P#57 size=1024KiB linesize=64 ways=16)
L1dCache L#29 (P#57 size=32KiB linesize=64 ways=8)
L1iCache L#29 (P#57 size=32KiB linesize=64 ways=8)
Core L#29 (P#25)
PU L#58 (P#37)
PU L#59 (P#77)
Group0 L#3 (total=372GiB)
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L2Cache L#30 (P#36 size=1024KiB linesize=64 ways=16)
L1dCache L#30 (P#36 size=32KiB linesize=64 ways=8)
L1iCache L#30 (P#36 size=32KiB linesize=64 ways=8)
Core L#30 (P#4)
PU L#60 (P#3)
PU L#61 (P#43)
L2Cache L#31 (P#35 size=1024KiB linesize=64 ways=16)
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L1iCache L#31 (P#35 size=32KiB linesize=64 ways=8)
Core L#31 (P#3)
PU L#62 (P#7)
PU L#63 (P#47)
L2Cache L#32 (P#44 size=1024KiB linesize=64 ways=16)
L1dCache L#32 (P#44 size=32KiB linesize=64 ways=8)
L1iCache L#32 (P#44 size=32KiB linesize=64 ways=8)
Core L#32 (P#12)
PU L#64 (P#11)
PU L#65 (P#51)
L2Cache L#33 (P#43 size=1024KiB linesize=64 ways=16)
L1dCache L#33 (P#43 size=32KiB linesize=64 ways=8)
L1iCache L#33 (P#43 size=32KiB linesize=64 ways=8)
Core L#33 (P#11)
PU L#66 (P#15)
PU L#67 (P#55)
L2Cache L#34 (P#42 size=1024KiB linesize=64 ways=16)
L1dCache L#34 (P#42 size=32KiB linesize=64 ways=8)
L1iCache L#34 (P#42 size=32KiB linesize=64 ways=8)
Core L#34 (P#10)
PU L#68 (P#19)
PU L#69 (P#59)
L2Cache L#35 (P#52 size=1024KiB linesize=64 ways=16)
L1dCache L#35 (P#52 size=32KiB linesize=64 ways=8)
L1iCache L#35 (P#52 size=32KiB linesize=64 ways=8)
Core L#35 (P#20)
PU L#70 (P#23)
PU L#71 (P#63)
L2Cache L#36 (P#51 size=1024KiB linesize=64 ways=16)
L1dCache L#36 (P#51 size=32KiB linesize=64 ways=8)
L1iCache L#36 (P#51 size=32KiB linesize=64 ways=8)
Core L#36 (P#19)
PU L#72 (P#27)
PU L#73 (P#67)
L2Cache L#37 (P#60 size=1024KiB linesize=64 ways=16)
L1dCache L#37 (P#60 size=32KiB linesize=64 ways=8)
L1iCache L#37 (P#60 size=32KiB linesize=64 ways=8)
Core L#37 (P#28)
PU L#74 (P#31)
PU L#75 (P#71)
L2Cache L#38 (P#59 size=1024KiB linesize=64 ways=16)
L1dCache L#38 (P#59 size=32KiB linesize=64 ways=8)
L1iCache L#38 (P#59 size=32KiB linesize=64 ways=8)
Core L#38 (P#27)
PU L#76 (P#35)
PU L#77 (P#75)
L2Cache L#39 (P#58 size=1024KiB linesize=64 ways=16)
L1dCache L#39 (P#58 size=32KiB linesize=64 ways=8)
L1iCache L#39 (P#58 size=32KiB linesize=64 ways=8)
Core L#39 (P#26)
PU L#78 (P#39)
PU L#79 (P#79)
depth 0: 1 Machine (type #0)
depth 1: 2 Package (type #1)
depth 2: 2 L3Cache (type #6)
depth 3: 4 Group0 (type #12)
depth 4: 40 L2Cache (type #5)
depth 5: 40 L1dCache (type #4)
depth 6: 40 L1iCache (type #9)
depth 7: 40 Core (type #2)
depth 8: 80 PU (type #3)
Special depth -3: 4 NUMANode (type #13)
Special depth -8: 4 MemCache (type #18)
Relative latency matrix (name NUMALatency kind 5) between 4 NUMANodes (depth -3) by logical indexes:
index 0 2 1 3
0 10 21 11 21
2 21 10 21 11
1 11 21 10 21
3 21 11 21 10
Topology infos: LinuxCgroup=/ Backend=Linux OSName=Linux OSRelease=5.3.0-rc7 OSVersion="#4 SMP Wed Sep 4 19:32:09 CEST 2019" HostName=leonide Architecture=x86_64
Topology not from this system
Binary file added tests/hwloc/linux/memorysidecaches.tar.bz2
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4 changes: 4 additions & 0 deletions tests/hwloc/linux/memorysidecaches.test
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# dual CascadeLake with DDR as Cache in front of Optane (2LM), SNC2
# 80intel64-2p2n20c2t
source: memorysidecaches.tar.bz2
target: memorysidecaches.console

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