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lstopo.1: clarify the documentation about PCI link speed in the graph…
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…ical output

Refs #528

Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
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bgoglin committed Apr 2, 2022
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Showing 1 changed file with 8 additions and 7 deletions.
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Expand Up @@ -657,18 +657,19 @@ their PCI bus ID (such as 00:02.3).
They may also contain sub-boxes for OS device objects
such as a network interface \fIeth0\fR or a CUDA GPU \fIcuda0\fR.

The datarate of a PCI link may be written (in GB/s) right below
its drawn line (if the operating system and/or libraries are able
to report that information).
This datarate is the currently configured PCI datarate.
It may change during execution since some devices are able to
slow their PCI links down when idle.

When there is a single link (horizontal line) on the right of a
PCI bridge, it means that a single device or bridge is connected
on the secondary PCI bus behind that bridge.
When there is a vertical line, it means that multiple devices
and/or bridges are connected to the same secondary PCI bus.

The datarate of a PCI link may be written (in GB/s) right below
its drawn line (if the operating system and/or libraries are able
to report that information).
This datarate is the currently configured speed of the entire PCI link
(sum of the bandwidth of all PCI lanes in that link).
It may change during execution since some devices are able to
slow their PCI links down when idle.
.
.\" **************************
.\" Layout Section
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