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dp16.C
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dp16.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file dp16.C
/// @brief Static data and subroutines to control the DP16 logic blocks
///
// *HWP HWP Owner: Jacob L Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <lib/shared/nimbus_defaults.H>
#include <fapi2.H>
#include <utility>
#include <vector>
#include <map>
#include <p9_mc_scom_addresses.H>
#include <p9_mc_scom_addresses_fld.H>
#include <lib/mss_attribute_accessors.H>
#include <lib/phy/dp16.H>
#include <lib/phy/write_cntrl.H>
#include <lib/utils/bit_count.H>
#include <lib/dimm/rank.H>
#include <generic/memory/lib/utils/scom.H>
#include <generic/memory/lib/utils/pos.H>
#include <generic/memory/lib/utils/c_str.H>
#include <lib/utils/find_magic.H>
#include <lib/ccs/ccs_traits_nimbus.H>
#include <lib/dimm/mrs_traits_nimbus.H>
#include <lib/workarounds/dp16_workarounds.H>
#include <lib/fir/check.H>
#include <generic/memory/lib/utils/mss_math.H>
using fapi2::TARGET_TYPE_MCS;
using fapi2::TARGET_TYPE_MCA;
using fapi2::TARGET_TYPE_DIMM;
using fapi2::TARGET_TYPE_MCBIST;
using fapi2::TARGET_TYPE_SYSTEM;
namespace mss
{
// Definition of the DP16 DLL Config registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DLL_CNFG_REG =
{
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4,
};
// Definition of the DP16 DLL Control registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Control Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_0, MCA_DDRPHY_DP16_DLL_CNTL1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_1, MCA_DDRPHY_DP16_DLL_CNTL1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_2, MCA_DDRPHY_DP16_DLL_CNTL1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_3, MCA_DDRPHY_DP16_DLL_CNTL1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_4, MCA_DDRPHY_DP16_DLL_CNTL1_P0_4 },
};
// Definition of the DP16 DLL DAC Lower registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_DAC_LOWER_REG =
{
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4 },
};
// Definition of the DP16 DLL DAC Upper registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_DAC_UPPER_REG =
{
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4 },
};
// Definition of the DP16 DLL Slave Lower registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_SLAVE_LOWER_REG =
{
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4 },
};
// Definition of the DP16 DLL Slave Upper registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_SLAVE_UPPER_REG =
{
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4 },
};
// Definition of the DP16 DLL SW Control registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_SW_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4 },
};
// Definition of the DP16 DLL VREG Coarse registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_VREG_COARSE_REG =
{
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4 },
};
// Definition of the DP16 DLL VREG Control registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_VREG_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4 },
};
// Definition of the DP16 DLL Extra registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_EXTRA_REG =
{
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4 },
};
// Definition of the DP16 Data Bit Dir1 registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_DIR1_REG
{
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4,
};
// Definition of the DP16 AC Boost Control registers
// DP16 AC Boost registers all come in pairs - one per 8 bits
// 5 DP16 per MCA gives us 10 Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::AC_BOOST_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4 },
};
// Definition of the DP16 CTLE Control registers
// DP16 CTLE Control registers all come in pairs - one per 8 bits
// 5 DP16 per MCA gives us 10 Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::CTLE_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4 },
};
// Definition of the IO TX FET slice registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_REG
{
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4,
};
// Definition of the IO TX PFET slice registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::IO_TX_PFET_TERM_REG
{
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4,
};
// Receiver configuration for the DP16.
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DP16_RX_REGS
{
{
MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0,
MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1,
MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2,
MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3,
MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4,
},
};
// Definition of the DD1 DP16 RD_VREF Control registers
// Note: For DD2 if we use the DD2_PERBIT_RDVREF_DISABLE, then these registers are still valid
// DP16 RD_VREF Control registers all come in pairs - one per 8 bits
// 5 DP16 per MCA gives us 10 Registers.
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DD1_RD_VREF_CNTRL_REG =
{
{
MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0 ,
MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1 ,
MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2 ,
MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3 ,
MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4
},
};
// Definition of the DD2 DP16 RD_VREF Control registers
// Note: DO NOT use this for DD1 as it will lead to a runtime scom access error
// DD2 DP16 RD_VREF Control registers all come in one register per pair of bits
// One register per two bits DP16 per MCA gives us 36 Registers.
// TK update the below constants with the DD2 register fixes
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DD2_RD_VREF_CNTRL_REG =
{
{
// DP0
MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0,
MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0,
MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0,
MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0,
MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0,
MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0,
MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0,
MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0,
// DP1
MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1,
MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1,
MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1,
MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1,
MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1,
MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1,
MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1,
MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1,
// DP2
MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2,
MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2,
MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2,
MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2,
MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2,
MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2,
MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2,
MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2,
// DP3
MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3,
MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3,
MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3,
MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3,
MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3,
MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3,
MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3,
MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3,
// DP4 - we only have 8 bits here, so 4 registers
MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4,
MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4,
MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4,
MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4,
},
};
// Definition of the DP16 DRIFT_LIMITS registers
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DRIFT_LIMITS_REG =
{
MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0,
MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1,
MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2,
MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3,
MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4,
};
// Definition of the DP16 RD_VREF Calibration enable registers
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_VREF_CAL_ENABLE_REG =
{
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4,
};
// Definition of the DP16 RD_VREF Calibration enable registers
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_VREF_CAL_ERROR_REG =
{
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4,
};
// Definition of the DP16 Phase Rotator Static Offset registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::PR_STATIC_OFFSET_REG
{
MCA_DDRPHY_DP16_WRCLK_PR_P0_0,
MCA_DDRPHY_DP16_WRCLK_PR_P0_1,
MCA_DDRPHY_DP16_WRCLK_PR_P0_2,
MCA_DDRPHY_DP16_WRCLK_PR_P0_3,
MCA_DDRPHY_DP16_WRCLK_PR_P0_4,
};
//////////////////////////////////////
// Defines all WR VREF registers //
//////////////////////////////////////
// Definition of the WR VREF config0 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_CONFIG0_REG =
{
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4,
};
// Definition of the WR VREF config1 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_CONFIG1_REG =
{
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4,
};
// Definition of the WR VREF status0 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_STATUS0_REG =
{
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4,
};
// Definition of the WR VREF status1 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_STATUS1_REG =
{
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4,
};
// Definition of the error mask registers element is DP16 number, first is mask 0 second is mask 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_ERROR_MASK_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4 },
};
// Definition of the error registers element is DP16 number, first is error 0 second is error 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_ERROR_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4 },
};
// Definition of the VREF value registers for RP0 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP0_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4 },
};
// Definition of the VREF value registers for RP1 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP1_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4 },
};
// Definition of the VREF value registers for RP2 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP2_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 },
};
// Definition of the VREF value registers for RP3 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP3_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 },
};
// Definition of the windage value registers per MCA. These are per rank pair, per DP16 and there are 2.
const std::vector<uint64_t> dp16Traits<TARGET_TYPE_MCA>::READ_DELAY_OFFSET_REG =
{
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4,
};
// Definition of the DISABLE registers, per dp per rank pair
const std::vector< std::vector<std::pair<uint64_t, uint64_t>> > dp16Traits<TARGET_TYPE_MCA>::BIT_DISABLE_REG =
{
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4 },
},
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4 },
},
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4 },
},
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4 },
},
};
// we need these declarations here in order for the linker to see the definitions
constexpr const uint64_t dp16Traits<fapi2::TARGET_TYPE_MCA>::GATE_DELAY_BIT_POS[];
constexpr const uint64_t dp16Traits<fapi2::TARGET_TYPE_MCA>::BLUE_WATERFALL_BIT_POS[];
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_ENABLE0_REG =
{
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_ENABLE1_REG =
{
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_DIA_CONFIG5_REG =
{
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_LVL_STATUS0_REG =
{
MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0,
MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1,
MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2,
MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3,
MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_LVL_STATUS2_REG =
{
MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0,
MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1,
MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2,
MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3,
MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_STATUS0_REG =
{
MCA_DDRPHY_DP16_RD_STATUS0_P0_0,
MCA_DDRPHY_DP16_RD_STATUS0_P0_1,
MCA_DDRPHY_DP16_RD_STATUS0_P0_2,
MCA_DDRPHY_DP16_RD_STATUS0_P0_3,
MCA_DDRPHY_DP16_RD_STATUS0_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_ERROR0_REG =
{
MCA_DDRPHY_DP16_WR_ERROR0_P0_0,
MCA_DDRPHY_DP16_WR_ERROR0_P0_1,
MCA_DDRPHY_DP16_WR_ERROR0_P0_2,
MCA_DDRPHY_DP16_WR_ERROR0_P0_3,
MCA_DDRPHY_DP16_WR_ERROR0_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_ENABLE1 =
{
MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4,
};
// Definition of the READ_DELAY registers, per rank pair
const std::vector< std::vector<uint64_t> > dp16Traits<TARGET_TYPE_MCA>::READ_DELAY_REG =
{
{
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4,
},
{
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4,
},
{
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4,
},
{
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4,
MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4,
MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4,
MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4,
},
};
// Definition of the READ_EYE_SIZE registers, per rank pair
const std::vector< std::vector<uint64_t> > dp16Traits<TARGET_TYPE_MCA>::READ_EYE_SIZE_REG =
{
{
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4,
},
{
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4,
},
{
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4,
},
{
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1,