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p9_mss_setup_bars.C
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p9_mss_setup_bars.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2020 */
/* [+] Inspur Power Systems Corp. */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
/// ----------------------------------------------------------------------------
/// @file p9_mss_setup_bars.H
///
/// @brief Program memory controller base address registers (BARs)
///
/// ----------------------------------------------------------------------------
/// *HWP HWP Owner : Joe McGill <jmcgill@us.ibm.com>
/// *HWP FW Owner : Thi Tran <thi@us.ibm.com>
/// *HWP Team : Nest
/// *HWP Level : 3
/// *HWP Consumed by : HB
/// ----------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <p9_mss_setup_bars.H>
#include <p9_mss_eff_grouping.H>
#include <p9_mc_scom_addresses.H>
#include <p9_mc_scom_addresses_fld.H>
#include <p9n2_mc_scom_addresses.H>
#include <p9n2_mc_scom_addresses_fld.H>
#include <p9a_mc_scom_addresses.H>
#include <p9a_mc_scom_addresses_fld.H>
#include <p9a_misc_scom_addresses.H>
#include <p9a_misc_scom_addresses_fld.H>
#include <p9a_addr_ext.H>
#include <map>
#include <lib/shared/mss_const.H>
#include <generic/memory/lib/utils/memory_size.H>
#include <lib/inband/exp_inband.H>
///----------------------------------------------------------------------------
/// Constant definitions
///----------------------------------------------------------------------------
const uint8_t USTL_MDI_EQUAL_ONE = 1;
const uint8_t MAX_MC_PORTS_PER_MCS = 2; // 2 MC ports per MCS
const uint8_t NO_CHANNEL_PER_GROUP = 0xFF; // Init value of channel per group
const uint32_t GEMINI_GLOBAL_CL_DISABLE = 0x3C0; //Gemini can't handle too many operations at once
const uint8_t GEMINI_FINE_CL_DISABLE = 0x3F ;
///----------------------------------------------------------------------------
/// Data structure definitions
///----------------------------------------------------------------------------
///
/// @struct channel_per_group_t
/// @brief Table of Channel Per Group value in MCFGP reg based on
/// the # of ports in group of ports 0 and 1 of an MCS.
///
static const struct channelPerGroupTable_t
{
uint8_t port0_ports_in_group;
uint8_t port1_ports_in_group;
uint8_t channel_per_group;
} CHANNEL_PER_GROUP_TABLE[] =
{
// Port 0 Port 1 Channel/group value
{ 1, 1, 0b0000 }, // 1 MC port/group for both port0 and port1
{ 1, 3, 0b0001 }, // 1 MC port/group for port0, 3 MC port/group for port1
{ 2, 1, 0b0100 }, // 2 MC port/group different MC port pairs
{ 3, 1, 0b0010 }, // 3 MC port/group for port0, 1 MC port/group for port1
{ 3, 3, 0b0011 }, // 3 MC port/group for port0, 3 MC port/group for port1
{ 2, 2, 0b0101 }, // 2 MC port/group in the same MC port pairs (Need additional verification in code below)
{ 2, 3, 0b0100 }, // 2 MC port/group different MC port pairs
{ 1, 2, 0b0100 }, // 2 MC port/group different MC port pairs
{ 3, 2, 0b0100 }, // 2 MC port/group different MC port pairs
{ 4, 4, 0b0110 }, // 4 MC ports/group, two ports in the same MC pairs
{ 6, 6, 0b0111 }, // 6 MC ports/group, two ports in the same MC pairs
{ 8, 8, 0b1000 }, // 8 MC ports/group, two ports in the same MC pairs
};
///
/// @struct group_size_t
/// @brief Table that determines MCFGP/MCFGPM bits 13:23 based on the group size.
///
static const struct groupSizeTable_t
{
// System attributes
uint32_t groupSize;
uint32_t encodedGroupSize;
} GROUP_SIZE_TABLE[] =
{
// GroupSize Encoded GroupSize
{ 4, 0b00000000000 }, // 4 GB
{ 8, 0b00000000001 }, // 8 GB
{ 16, 0b00000000011 }, // 16 GB
{ 32, 0b00000000111 }, // 32 GB
{ 64, 0b00000001111 }, // 64 GB
{ 128, 0b00000011111 }, // 128 GB
{ 256, 0b00000111111 }, // 256 GB
{ 512, 0b00001111111 }, // 512 GB
{ 1024, 0b00011111111 }, // 1 TB
{ 2048, 0b00111111111 }, // 2 TB
{ 4096, 0b01111111111 }, // 4 TB
{ 8192, 0b000011111111111 }, // 8 TB
{ 16384, 0b000111111111111 }, // 16 TB
{ 32768, 0b001111111111111 }, // 32 TB
{ 65536, 0b011111111111111 }, // 64 TB
{ 131072, 0b111111111111111 } // 128 TB
};
/**
* @struct mcPortGroupInfo_t
*
* Contains group data information related to a port (MCA/DMI).
* This information is used to determine the channel per group
* value for the MCFGP reg.
*
*/
struct mcPortGroupInfo_t
{
/**
* @brief Default constructor. Initializes instance variables to zero
*/
inline mcPortGroupInfo_t()
: myGroup(0), numPortsInGroup(0), groupSize(0), groupBaseAddr(0),
channelId(0), smfMemValid(0), smfMemSize(0), smfBaseAddr(0)
{
memset(altMemValid, 0, sizeof(altMemValid));
memset(altMemSize, 0, sizeof(altMemSize));
memset(altBaseAddr, 0, sizeof(altBaseAddr));
}
// The group number which this port belongs to
uint8_t myGroup;
// # of ports in the group which this port belongs to.
uint8_t numPortsInGroup;
// The size of the group which this port belongs to
uint32_t groupSize;
// The base address of the group which this port belongs to
uint32_t groupBaseAddr;
// The group member ID of this port
uint8_t channelId;
// ALT_MEM
uint8_t altMemValid[NUM_OF_ALT_MEM_REGIONS];
uint32_t altMemSize[NUM_OF_ALT_MEM_REGIONS];
uint32_t altBaseAddr[NUM_OF_ALT_MEM_REGIONS];
// SMF_MEM
uint8_t smfMemValid;
uint32_t smfMemSize;
uint32_t smfBaseAddr;
};
/**
* @struct mcBarData_t
*
* Contains BAR data info for a Memory Controller (MCS/MI)
*/
struct mcBarData_t
{
/**
* @brief Default constructor. Initializes instance variables to zero
*/
inline mcBarData_t()
: MCFGP_valid(false), MCFGP_chan_per_group(0),
MCFGP_chan0_group_member_id(0), MCFGP_chan1_group_member_id(0),
MCFGP_group_size(0), MCFGP_groupBaseAddr(0),
MCFGPM_valid(false), MCFGPM_group_size(0), MCFGPM_groupBaseAddr(0),
MCFGPA_SMF_valid(0), MCFGPA_SMF_LOWER_addr(0), MCFGPA_SMF_UPPER_addr(0),
MCFGPMA_SMF_valid(0), MCFGPMA_SMF_LOWER_addr(0), MCFGPMA_SMF_UPPER_addr(0)
{
memset(MCFGPA_HOLE_valid, 0, sizeof(MCFGPA_HOLE_valid));
memset(MCFGPA_HOLE_LOWER_addr, 0, sizeof(MCFGPA_HOLE_LOWER_addr));
memset(MCFGPA_HOLE_UPPER_addr, 0, sizeof(MCFGPA_HOLE_UPPER_addr));
memset(MCFGPMA_HOLE_valid, 0, sizeof(MCFGPMA_HOLE_valid));
memset(MCFGPMA_HOLE_LOWER_addr, 0, sizeof(MCFGPMA_HOLE_LOWER_addr));
memset(MCFGPMA_HOLE_UPPER_addr, 0, sizeof(MCFGPMA_HOLE_UPPER_addr));
}
// Info to program MCFGP reg
bool MCFGP_valid;
uint8_t MCFGP_chan_per_group;
uint8_t MCFGP_chan0_group_member_id;
uint8_t MCFGP_chan1_group_member_id;
uint32_t MCFGP_group_size;
uint32_t MCFGP_groupBaseAddr;
// Info to program MCFGPM reg
bool MCFGPM_valid;
uint32_t MCFGPM_group_size;
uint32_t MCFGPM_groupBaseAddr;
// Info to program MCFGPA reg
bool MCFGPA_HOLE_valid[NUM_OF_ALT_MEM_REGIONS];
uint32_t MCFGPA_HOLE_LOWER_addr[NUM_OF_ALT_MEM_REGIONS];
uint32_t MCFGPA_HOLE_UPPER_addr[NUM_OF_ALT_MEM_REGIONS];
bool MCFGPA_SMF_valid;
uint32_t MCFGPA_SMF_LOWER_addr;
uint32_t MCFGPA_SMF_UPPER_addr;
// Info to program MCFGPMA reg
bool MCFGPMA_HOLE_valid[NUM_OF_ALT_MEM_REGIONS];
uint32_t MCFGPMA_HOLE_LOWER_addr[NUM_OF_ALT_MEM_REGIONS];
uint32_t MCFGPMA_HOLE_UPPER_addr[NUM_OF_ALT_MEM_REGIONS];
bool MCFGPMA_SMF_valid;
uint32_t MCFGPMA_SMF_LOWER_addr;
uint32_t MCFGPMA_SMF_UPPER_addr;
};
///----------------------------------------------------------------------------
/// Function definitions
///----------------------------------------------------------------------------
///
/// @brief Get MC(MCS/MI) position for the input PORT_ID
///
/// PORT_ID 0 --> MC 0
/// PORT_ID 1 --> MC 0
/// PORT_ID 2 --> MC 1
/// PORT_ID 3 --> MC 1
/// PORT_ID 4 --> MC 2
/// PORT_ID 5 --> MC 2
/// PORT_ID 6 --> MC 3
/// PORT_ID 7 --> MCS 3
///
/// @param[in] i_portID PortID
/// @return MC position
///
uint8_t getMCPosition(uint8_t i_portID)
{
return (i_portID / 2);
}
///
/// @brief Get the port number (with respect to the MC, 0 or 1) for the
/// input PORT_ID
///
/// PORT_ID 0 --> MCS port 0
/// PORT_ID 1 --> MCS port 1
/// PORT_ID 2 --> MCS port 0
/// PORT_ID 3 --> MCS port 1
/// PORT_ID 4 --> MCS port 0
/// PORT_ID 5 --> MCS port 1
/// PORT_ID 6 --> MCS port 0
/// PORT_ID 7 --> MCS port 1
///
/// @param[in] i_portID PortID
/// @return port num
///
uint8_t getMCPortNum(uint8_t i_portID)
{
uint8_t l_mcPos = getMCPosition(i_portID);
return (i_portID - (2 * l_mcPos));
}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
///
/// @brief Get the memory size behind a Memory controller
/// by calling into mss library.
///
/// @param[in] i_target MC target (MCS or MI)
/// @param[out] o_mcSize The total mem size found
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
template<fapi2::TargetType T>
fapi2::ReturnCode getMcMemSize(const fapi2::Target<T>& i_target,
uint64_t& o_mcSize);
/// MC = MCS (Nimbus)
template<>
fapi2::ReturnCode getMcMemSize(
const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
uint64_t& o_mcSize)
{
FAPI_DBG("Entering");
// Figure out the amount of memory behind this MCS
// by adding up all memory from its MCA ports
auto l_mcaChiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCA>();
uint64_t l_mcaSize = 0;
for (auto l_mca : l_mcaChiplets)
{
uint8_t l_mcaPos = 0;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mca, l_mcaPos),
"Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Get the amount of memory behind this MCA target
FAPI_TRY(mss::eff_memory_size<mss::mc_type::NIMBUS>(l_mca, l_mcaSize),
"Error returned from eff_memory_size - MCA, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
FAPI_INF("MCA %u: Total DIMM size %lu GB", l_mcaPos, l_mcaSize);
o_mcSize += l_mcaSize;
}
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
/// MC = MI (Cumulus)
template<>
fapi2::ReturnCode getMcMemSize(
const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_target,
uint64_t& o_mcSize)
{
FAPI_DBG("Entering");
// Figure out the amount of memory behind this MI
// by adding up all memory from its DMI ports
auto l_dmiChiplets = i_target.getChildren<fapi2::TARGET_TYPE_DMI>();
uint64_t l_chSize = 0;
for (auto l_dmi : l_dmiChiplets)
{
uint8_t l_dmiPos = 0;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_dmi, l_dmiPos),
"Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Get the amount of memory behind this DMI target
FAPI_TRY(mss::eff_memory_size<mss::mc_type::CENTAUR>(l_dmi, l_chSize),
"Error returned from eff_memory_size - DMI, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
FAPI_INF("DMI %u: Total DIMM size %lu GB", l_dmiPos, l_chSize);
o_mcSize += l_chSize;
}
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
/// MC = MCC (Axone)
template<>
fapi2::ReturnCode getMcMemSize(
const fapi2::Target<fapi2::TARGET_TYPE_MCC>& i_target,
uint64_t& o_mcSize)
{
FAPI_DBG("Entering");
// Figure out the amount of memory behind this MI
// by adding up all memory from its OMI ports
uint64_t l_chSize = 0;
uint64_t l_sub_size[SUBCHANNEL_PER_CHANNEL];
uint64_t l_sub_minsize = 0;
uint64_t l_num_sub = 0;
auto l_omiChiplets = i_target.getChildren<fapi2::TARGET_TYPE_OMI>();
memset(l_sub_size, 0, sizeof(l_sub_size));
for (auto l_omi : l_omiChiplets)
{
const auto& l_ocmb_chips = l_omi.getChildren<fapi2::TARGET_TYPE_OCMB_CHIP>();
if (!l_ocmb_chips.empty())
{
uint8_t l_omiPos = 0;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_omi, l_omiPos),
"Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Get the amount of memory behind this OMI
FAPI_TRY(mss::eff_memory_size<mss::mc_type::EXPLORER>(l_ocmb_chips[0], l_chSize),
"Error returned from eff_memory_size - ocmb, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
FAPI_INF("OMI %u: Total DIMM size %lu GB", l_omiPos, l_chSize);
l_sub_size[l_omiPos % SUBCHANNEL_PER_CHANNEL] = l_chSize;
if (l_chSize > 0)
{
l_num_sub++;
if (l_sub_minsize == 0 || l_sub_minsize > l_chSize)
{
l_sub_minsize = l_chSize;
}
}
}
}
l_chSize = (l_num_sub * l_sub_minsize);
o_mcSize += l_chSize;
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
///
/// @brief Calculate the memory size behind a Memory controller
/// from group data.
///
/// @param[in] i_mcPos MC position
/// @param[in] i_omi Chip uses OMI?
/// @param[in] i_groupData Array of Group data info
/// @param[out] o_portFound Mark how many time a port is found.
/// @param[out] o_mcSize The total mem size calculated
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
void getGroupDataMcMemSize(
uint8_t i_mcPos,
const bool i_omi,
const uint32_t i_groupData[DATA_GROUPS][DATA_ELEMENTS],
uint8_t o_portFound[NUM_MC_PORTS_PER_PROC],
uint64_t& o_mcSize)
{
FAPI_DBG("Entering");
// Loop thru non-mirror groups (0-7)
for (uint8_t l_group = 0; l_group < (DATA_GROUPS / 2); l_group++)
{
// Skip empty groups
if (i_groupData[l_group][GROUP_SIZE] == 0)
{
continue;
}
// Loop thru the group port member index to determine if the
// PORT_ID listed belongs to this MCS
for (uint8_t l_memberIdx = 0;
l_memberIdx < i_groupData[l_group][PORTS_IN_GROUP]; l_memberIdx++)
{
// If the PORT_ID listed belongs to this MC, add the amount
// of memory behind the port to this MC.
uint8_t l_mcId = getMCPosition(i_groupData[l_group][MEMBER_IDX(0) +
l_memberIdx]);
if ((!i_omi && l_mcId == i_mcPos) ||
(i_omi && i_mcPos == i_groupData[l_group][MEMBER_IDX(0) + l_memberIdx]))
{
o_mcSize += i_groupData[l_group][PORT_SIZE];
FAPI_INF("getGroupDataMcMemSize - Port %u, DIMM size %lu GB",
i_groupData[l_group][MEMBER_IDX(0) + l_memberIdx],
i_groupData[l_group][PORT_SIZE]);
// Increase # of times this PORT_ID is found
o_portFound[i_groupData[l_group][MEMBER_IDX(0) + l_memberIdx]]++;
}
} // Port loop
} // Group loop
FAPI_DBG("Exit");
return;
}
///
/// @brief Validate group data received from ATTR_MSS_MCS_GROUP_32
///
/// Perform these verifications:
/// - The memory sizes of MCS/MI in the input group data
/// agrees with with the amount memory currently reported.
/// - An MCA/DMMI port can only appear once in any group.
///
/// @param[in] i_mcTargets Vector of reference of MC targets (MCS or MI)
/// @param[in] i_omi Chip uses OMI?
/// @param[in] i_groupData Array of Group data info
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
template<fapi2::TargetType T>
fapi2::ReturnCode validateGroupData(
const std::vector< fapi2::Target<T> >& i_mcTargets,
const bool i_omi,
const uint32_t i_groupData[DATA_GROUPS][DATA_ELEMENTS])
{
FAPI_DBG("Entering");
uint64_t l_mcSize = 0;
uint64_t l_mcSizeGroupData = 0;
uint8_t l_portFound[NUM_MC_PORTS_PER_PROC];
// Initialize local arrays
memset(l_portFound, 0, sizeof(l_portFound));
// Loop thru each MC
for (auto l_mc : i_mcTargets)
{
// Get this MCS unit position
uint8_t l_mcPos = 0;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mc, l_mcPos),
"Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
FAPI_INF("validateGroupData: MC unit pos %d", l_mcPos);
// Get the memory size behind this MC
FAPI_TRY(getMcMemSize(l_mc, l_mcSize),
"Error returned from getMcMemSize, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Get this MC memsize reported in Group data
getGroupDataMcMemSize(l_mcPos, i_omi, i_groupData, l_portFound,
l_mcSizeGroupData);
FAPI_DBG("validateGroupData: MemSize %.16lld, Group Memsize %.16lld",
l_mcSize, l_mcSizeGroupData);
// Assert if MC specified in Group data doesn't agree
// with the amount gets from Memory interface.
FAPI_ASSERT(l_mcSizeGroupData == l_mcSize,
fapi2::MSS_SETUP_BARS_MC_MEMSIZE_DISCREPENCY()
.set_TARGET(l_mc)
.set_MC_POS(l_mcPos)
.set_MEMSIZE_GROUP_DATA(l_mcSizeGroupData)
.set_MEMSIZE_REPORTED(l_mcSize),
"Error: MCS %u memory discrepancy: Group data size %u, "
"Current memory reported %u",
l_mcPos, l_mcSizeGroupData, l_mcSize);
} // MC loop
FAPI_INF("Total memory size= %lu GB", l_mcSize);
// Assert if a PORT_ID is found more than once in any group
for (uint8_t ii = 0; ii < NUM_MC_PORTS_PER_PROC; ii++)
{
// Assert if a PORT_ID is found more than once in any group
FAPI_ASSERT(l_portFound[ii] <= 1,
fapi2::MSS_SETUP_BARS_MULTIPLE_GROUP_ERR()
.set_PORT_ID(ii)
.set_COUNTER(l_portFound[ii]),
"Error: PORT_ID %u is grouped multiple times. "
"Port %d, Counter %u", ii, l_portFound[ii]);
}
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
///
/// @brief Look up table to determine the MCFGP/MCFGPM group size
/// encoded value (bits 13:23).
///
/// @param[in] i_mcTarget MC target (MCS/MI)
/// @param[in] i_groupSize Group size (in GB)
/// @param[out] o_value Encoded value
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
template<fapi2::TargetType T>
fapi2::ReturnCode getGroupSizeEncodedValue(
const fapi2::Target<T>& i_mcTarget,
const uint32_t i_groupSize,
uint32_t& o_value)
{
FAPI_DBG("Entering");
bool l_sizeFound = false;
for (uint8_t ii = 0;
ii < (sizeof(GROUP_SIZE_TABLE) / sizeof(groupSizeTable_t));
ii++)
{
if ( i_groupSize == GROUP_SIZE_TABLE[ii].groupSize)
{
o_value = GROUP_SIZE_TABLE[ii].encodedGroupSize;
l_sizeFound = true;
break;
}
}
if (l_sizeFound == false)
{
uint8_t l_mcPos = 0;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_mcTarget, l_mcPos),
"Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Assert if can't find Group size in the table
FAPI_ASSERT( false,
fapi2::MSS_SETUP_BARS_INVALID_GROUP_SIZE()
.set_MC_TARGET(i_mcTarget)
.set_MC_POS(l_mcPos)
.set_GROUP_SIZE(i_groupSize),
"Error: Can't locate Group size value in GROUP_SIZE_TABLE. "
"MC pos: %d, GroupSize %u GB.", l_mcPos, i_groupSize );
}
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
///
/// @brief Calculate the BAR data for each MC (MCS/MI) based on group info
/// of port0/1
///
/// @param[in] i_mcTarget MC target (MCS/MI)
/// @param[in] i_portInfo The port group info
/// @param[in] o_mcBarData MC BAR data
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
template<fapi2::TargetType T>
fapi2::ReturnCode getNonMirrorBarData(const fapi2::Target<T>& i_mcTarget,
const mcPortGroupInfo_t i_portInfo[],
mcBarData_t& o_mcBarData)
{
FAPI_DBG("Entering");
// This function assign the MCFGP_MC_CHANNELS_PER_GROUP value
// to the MC according to the rule listed in the Nimbus/Cumulus workbook.
// Initialize
o_mcBarData.MCFGP_chan_per_group = NO_CHANNEL_PER_GROUP;
o_mcBarData.MCFGP_valid = false;
o_mcBarData.MCFGPM_valid = false;
// ----------------------------------------------------
// Determine data for MCFGP and MCFGPM registers
// ----------------------------------------------------
// Channel per group (MCFGP bits 1:4)
for (uint8_t ii = 0;
ii < (sizeof(CHANNEL_PER_GROUP_TABLE) / sizeof(channelPerGroupTable_t));
ii++)
{
uint8_t l_port0_lookup_val = i_portInfo[0].numPortsInGroup;
uint8_t l_port1_lookup_val = i_portInfo[1].numPortsInGroup;
// If port is disabled, treat as single port. However, this
// port will be set invalid in MCFGP reg further below
//
if (l_port0_lookup_val == 0)
{
l_port0_lookup_val = 1;
}
if (l_port1_lookup_val == 0)
{
l_port1_lookup_val = 1;
}
if ( (l_port0_lookup_val == CHANNEL_PER_GROUP_TABLE[ii].port0_ports_in_group) &&
(l_port1_lookup_val == CHANNEL_PER_GROUP_TABLE[ii].port1_ports_in_group) )
{
o_mcBarData.MCFGP_chan_per_group = CHANNEL_PER_GROUP_TABLE[ii].channel_per_group;
}
}
// Assert if ports 0/1 don't match any entry in table
FAPI_ASSERT(o_mcBarData.MCFGP_chan_per_group != NO_CHANNEL_PER_GROUP,
fapi2::MSS_SETUP_BARS_INVALID_PORTS_CONFIG()
.set_MC_TARGET(i_mcTarget)
.set_PORT_0_PORTS_IN_GROUP(i_portInfo[0].numPortsInGroup)
.set_PORT_0_GROUP(i_portInfo[0].myGroup)
.set_PORT_1_PORTS_IN_GROUP(i_portInfo[1].numPortsInGroup)
.set_PORT_1_GROUP(i_portInfo[1].myGroup),
"Error: ports 0/1 config doesn't match any entry in Channel/group table. "
"Port_0: group %u, ports in group %u, Port_1: group %u, ports in group %u",
i_portInfo[0].myGroup, i_portInfo[0].numPortsInGroup,
i_portInfo[1].myGroup, i_portInfo[1].numPortsInGroup);
// MCFGP valid (MCFGP bit 0)
if ( i_portInfo[0].numPortsInGroup == 0)
{
// Port0 not populated
o_mcBarData.MCFGP_valid = false;
}
else
{
// Port0 populated
o_mcBarData.MCFGP_valid = true;
}
// MCFGPM valid (MCFGPM bit 0)
if ( i_portInfo[1].numPortsInGroup == 0)
{
// Port1 not populated
o_mcBarData.MCFGPM_valid = false;
}
else
{
// MCFGPM is valid if Channel_per_group < 0b0101
if (o_mcBarData.MCFGP_chan_per_group < 0b0101)
{
o_mcBarData.MCFGPM_valid = true;
}
// Determine if MCFGPM valid when Channel_per_group = 0b0101
else if (o_mcBarData.MCFGP_chan_per_group == 0b0101)
{
// Port1 populated, 2 MC/group
// The table assigns 0b0101 if both ports belong 2 MC port/group,
// Here, verify that they belong to the same group, if not,
// re-assign the channel per group to 2 MC/group in different
// MC port pairs (0b0100)
if ( i_portInfo[0].myGroup != i_portInfo[1].myGroup )
{
o_mcBarData.MCFGP_chan_per_group = 0b0100;
o_mcBarData.MCFGPM_valid = true;
}
}
// MCFGPM is not valid if Channel_per_group > 0b0101
// (2,4,6 or 8, and in same MC port pair)
// This is true because mirroring is not supported on Nimbus.
// For Cumulus, mirroring will be checked/programmed later
// in another function.
else
{
o_mcBarData.MCFGPM_valid = false;
}
}
FAPI_TRY(getNonMirrorBarIdSize(i_mcTarget, i_portInfo, o_mcBarData));
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
///
/// @brief Calculate the BAR data for each MC (MCS/MI) based on group info
/// of port0/1
///
/// @param[in] i_mcTarget MC target (MCS/MI)
/// @param[in] i_portInfo The port group info
/// @param[in] o_mcBarData MC BAR data
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
template<fapi2::TargetType T>
fapi2::ReturnCode getNonMirrorBarIdSize(const fapi2::Target<T>& i_mcTarget,
const mcPortGroupInfo_t i_portInfo[],
mcBarData_t& o_mcBarData)
{
// MCFGP Channel_0 Group member ID (bits 5:7)
o_mcBarData.MCFGP_chan0_group_member_id = i_portInfo[0].channelId;
// MCFGP Channel_1 Group member ID (bits 8:10)
o_mcBarData.MCFGP_chan1_group_member_id = i_portInfo[1].channelId;
// If MCFGP is valid, set other fields
if (o_mcBarData.MCFGP_valid == true)
{
// MCFGP Group size
FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo[0].groupSize,
o_mcBarData.MCFGP_group_size),
"getGroupSizeEncodedValue() returns error, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Group base address
o_mcBarData.MCFGP_groupBaseAddr = i_portInfo[0].groupBaseAddr;
}
// If MCFGPM is valid, set other fields
if (o_mcBarData.MCFGPM_valid == true)
{
// MCFGPM Group size
FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo[1].groupSize,
o_mcBarData.MCFGPM_group_size),
"getGroupSizeEncodedValue() returns error, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Group base address
o_mcBarData.MCFGPM_groupBaseAddr = i_portInfo[1].groupBaseAddr;
}
// ----------------------------------------------------
// Determine data for MCFGPA and MCFGPMA registers
// ----------------------------------------------------
// Alternate Memory MCFGPA
for (uint8_t ii = 0; ii < NUM_OF_ALT_MEM_REGIONS; ii++)
{
if ( o_mcBarData.MCFGP_valid && i_portInfo[0].altMemValid[ii] )
{
o_mcBarData.MCFGPA_HOLE_valid[ii] = 1;
o_mcBarData.MCFGPA_HOLE_LOWER_addr[ii] = i_portInfo[0].altBaseAddr[ii];
o_mcBarData.MCFGPA_HOLE_UPPER_addr[ii] =
i_portInfo[0].altBaseAddr[ii] + i_portInfo[0].altMemSize[ii];
}
else
{
o_mcBarData.MCFGPA_HOLE_valid[ii] = 0;
o_mcBarData.MCFGPA_HOLE_LOWER_addr[ii] = 0;
o_mcBarData.MCFGPA_HOLE_UPPER_addr[ii] = 0;
}
if ( o_mcBarData.MCFGPM_valid && i_portInfo[1].altMemValid[ii] )
{
o_mcBarData.MCFGPMA_HOLE_valid[ii] = 1;
o_mcBarData.MCFGPMA_HOLE_LOWER_addr[ii] = i_portInfo[1].altBaseAddr[ii];
o_mcBarData.MCFGPMA_HOLE_UPPER_addr[ii] =
i_portInfo[1].altBaseAddr[ii] + i_portInfo[1].altMemSize[ii];
}
else
{
o_mcBarData.MCFGPMA_HOLE_valid[ii] = 0;
o_mcBarData.MCFGPMA_HOLE_LOWER_addr[ii] = 0;
o_mcBarData.MCFGPMA_HOLE_UPPER_addr[ii] = 0;
}
}
// SMF Section of MCFGPA and MCFGPMA
if ( o_mcBarData.MCFGP_valid && i_portInfo[0].smfMemValid )
{
o_mcBarData.MCFGPA_SMF_valid = 1;
o_mcBarData.MCFGPA_SMF_LOWER_addr = i_portInfo[0].smfBaseAddr;
o_mcBarData.MCFGPA_SMF_UPPER_addr = i_portInfo[0].smfBaseAddr + i_portInfo[0].smfMemSize;
}
else
{
o_mcBarData.MCFGPA_SMF_valid = 0;
o_mcBarData.MCFGPA_SMF_LOWER_addr = 0;
o_mcBarData.MCFGPA_SMF_UPPER_addr = 0;
}
if ( o_mcBarData.MCFGPM_valid && i_portInfo[1].smfMemValid )
{
o_mcBarData.MCFGPMA_SMF_valid = 1;
o_mcBarData.MCFGPMA_SMF_LOWER_addr = i_portInfo[1].smfBaseAddr;
o_mcBarData.MCFGPMA_SMF_UPPER_addr = i_portInfo[1].smfBaseAddr + i_portInfo[1].smfMemSize;
}
else
{
o_mcBarData.MCFGPMA_SMF_valid = 0;
o_mcBarData.MCFGPMA_SMF_LOWER_addr = 0;
o_mcBarData.MCFGPMA_SMF_UPPER_addr = 0;
}
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
///
/// @brief Calculate the BAR data for each MC (MCS/MI) based on group info
/// of port0/1
///
/// @param[in] i_mcTarget MC target (MCS/MI)
/// @param[in] i_portInfo The port group info
/// @param[in] o_mcBarData MC BAR data
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode getNonMirrorBarIdSize(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& i_mcTarget,
const mcPortGroupInfo_t& i_portInfo,
mcBarData_t& o_mcBarData)
{
// MCFGP Channel_0 Group member ID (bits 5:7)
o_mcBarData.MCFGP_chan0_group_member_id = i_portInfo.channelId;
// If MCFGP is valid, set other fields
if (o_mcBarData.MCFGP_valid == true)
{
// MCFGP Group size
FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo.groupSize,
o_mcBarData.MCFGP_group_size),
"getGroupSizeEncodedValue() returns error, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Group base address
o_mcBarData.MCFGP_groupBaseAddr = i_portInfo.groupBaseAddr;
}
// If MCFGPM is valid, set other fields
if (o_mcBarData.MCFGPM_valid == true)
{
// MCFGPM Group size
FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo.groupSize,
o_mcBarData.MCFGPM_group_size),
"getGroupSizeEncodedValue() returns error, l_rc 0x%.8X",
uint64_t(fapi2::current_err));
// Group base address
o_mcBarData.MCFGPM_groupBaseAddr = i_portInfo.groupBaseAddr;
}
// ----------------------------------------------------
// Determine data for MCFGPA and MCFGPMA registers
// ----------------------------------------------------
// Alternate Memory MCFGPA
for (uint8_t ii = 0; ii < NUM_OF_ALT_MEM_REGIONS; ii++)
{
if ( i_portInfo.altMemValid[ii] )
{
o_mcBarData.MCFGPA_HOLE_valid[ii] = 1;
o_mcBarData.MCFGPA_HOLE_LOWER_addr[ii] = i_portInfo.altBaseAddr[ii];
o_mcBarData.MCFGPA_HOLE_UPPER_addr[ii] =
i_portInfo.altBaseAddr[ii] + i_portInfo.altMemSize[ii];
}
else
{
o_mcBarData.MCFGPA_HOLE_valid[ii] = 0;
o_mcBarData.MCFGPA_HOLE_LOWER_addr[ii] = 0;
o_mcBarData.MCFGPA_HOLE_UPPER_addr[ii] = 0;
}
}
// SMF Section of MCFGPA and MCFGPMA
if ( i_portInfo.smfMemValid )
{
o_mcBarData.MCFGPA_SMF_valid = 1;
o_mcBarData.MCFGPA_SMF_LOWER_addr = i_portInfo.smfBaseAddr;
o_mcBarData.MCFGPA_SMF_UPPER_addr = i_portInfo.smfBaseAddr + i_portInfo.smfMemSize;
}
else
{
o_mcBarData.MCFGPA_SMF_valid = 0;
o_mcBarData.MCFGPA_SMF_LOWER_addr = 0;
o_mcBarData.MCFGPA_SMF_UPPER_addr = 0;
}
fapi_try_exit:
FAPI_DBG("Exit");
return fapi2::current_err;
}
///
/// @brief Calculate the BAR data for each MCC based on group info
/// of port0/1 - OMI specific
///
/// @param[in] i_mcTarget MC target (MCC)
/// @param[in] i_portInfo The port group info
/// @param[in] o_mcBarData MC BAR data
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode getNonMirrorBarData(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& i_mcTarget,
const mcPortGroupInfo_t& i_portInfo,
mcBarData_t& o_mcBarData)
{
FAPI_DBG("Entering");
// Initialize
o_mcBarData.MCFGP_chan_per_group = NO_CHANNEL_PER_GROUP;
o_mcBarData.MCFGP_valid = false;
o_mcBarData.MCFGPM_valid = false;
// MCFGP valid (MCFGP bit 0)
if ( i_portInfo.numPortsInGroup > 0)
{
o_mcBarData.MCFGP_valid = true;
o_mcBarData.MCFGPM_valid = false;
// ----------------------------------------------------
// Determine data for MCFGP and MCFGPM registers
// ----------------------------------------------------
if (i_portInfo.numPortsInGroup == 8)
{
o_mcBarData.MCFGP_chan_per_group = 0;
}
else if (i_portInfo.numPortsInGroup == 1 ||
i_portInfo.numPortsInGroup == 2 ||
i_portInfo.numPortsInGroup == 3 ||
i_portInfo.numPortsInGroup == 4 ||
i_portInfo.numPortsInGroup == 6 )
{
o_mcBarData.MCFGP_chan_per_group = i_portInfo.numPortsInGroup;
}
// Assert if ports 0/1 don't match any entry in table
FAPI_ASSERT(o_mcBarData.MCFGP_chan_per_group != NO_CHANNEL_PER_GROUP,
fapi2::MSS_SETUP_BARS_INVALID_PORTS_CONFIG()
.set_MC_TARGET(i_mcTarget)
.set_PORT_0_PORTS_IN_GROUP(i_portInfo.numPortsInGroup)
.set_PORT_0_GROUP(i_portInfo.myGroup)
.set_PORT_1_PORTS_IN_GROUP(0)
.set_PORT_1_GROUP(0),
"Error: Invalid number of ports per group"
"group %u, ports in group %u",
i_portInfo.myGroup, i_portInfo.numPortsInGroup);
}
FAPI_TRY(getNonMirrorBarIdSize(i_mcTarget, i_portInfo, o_mcBarData));