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mss_generic_attribute_getters.H
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mss_generic_attribute_getters.H
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/generic/memory/lib/mss_generic_attribute_getters.H $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
// mss_generic_attribute_getters.H
#ifndef MSS_GENERIC_ATTR_GETTERS_H_
#define MSS_GENERIC_ATTR_GETTERS_H_
#include <fapi2.H>
#include <generic/memory/lib/utils/index.H>
#include <generic/memory/lib/utils/c_str.H>
namespace mss
{
namespace attr
{
///
/// @brief ATTR_BAD_DQ_BITMAP getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_other_attr_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Bad DQ bitmap from a controller point of view. The data is a 10 byte bitmap for
/// each of 4 possible ranks. The bad DQ data is stored in NVRAM, and it is stored in
/// a special format translated to a DIMM Connector point of view. All of these details
/// are hidden from the user of this attribute.
///
inline fapi2::ReturnCode get_bad_dq_bitmap(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
uint8_t (&o_array)[4][10])
{
uint8_t l_value[4][10] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_BAD_DQ_BITMAP, i_target, l_value) );
memcpy(o_array, &l_value, 40);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_BAD_DQ_BITMAP: 0x%lx",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_POS_METADATA getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint32_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_other_attr_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note To get the FAPI_POS to the equivilent of ATTR_POS, we need to normalize the fapi_pos
/// value to the processor (stride across which ever processor we're on) and then add
/// in the delta per processor as ATTR_POS isn't processor relative (delta is the total
/// dimm on a processor)
///
inline fapi2::ReturnCode get_dimm_pos_metadata(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
uint32_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, o_value) );
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_POS_METADATA: 0x%lx",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DRAM_GEN_METADATA getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_other_attr_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note DRAM Device Type. Decodes SPD byte 2. Created for use by attributes that need this
/// data earlier than eff_config, such as c_str and the hypervisor. Not meant for direct
/// HWP use. This is just an abstraction of any chip specific EFF_DRAM_GEN attribute.
///
inline fapi2::ReturnCode get_dram_gen_metadata(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, o_value) );
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DRAM_GEN_METADATA: 0x%lx",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_TYPE_METADATA getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_other_attr_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Base Module Type. Decodes SPD Byte 3 (bits 3~0). Created for use by attributes that
/// need this data earlier than eff_config, such as c_str and the hypervisor. Not meant
/// for direct HWP use. This is just an abstraction of any chip specific EFF_DIMM_TYPE
/// attribute.
///
inline fapi2::ReturnCode get_dimm_type_metadata(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
uint8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, o_value) );
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_TYPE_METADATA: 0x%lx",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DRAM_CWL getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note CAS Write Latency.
///
inline fapi2::ReturnCode get_dram_cwl(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_CWL, i_target, o_value) );
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DRAM_CWL: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_RDIMM_BUFFER_DELAY getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Delay due to the presence of a buffer, in number of clocks
///
inline fapi2::ReturnCode get_dimm_buffer_delay(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_RDIMM_BUFFER_DELAY, i_target, o_value) );
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_RDIMM_BUFFER_DELAY: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_VPD_DQ_MAP getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin
/// to the Module Package Data (DQ) Pinout
///
inline fapi2::ReturnCode get_mem_vpd_dq_map(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[72])
{
uint8_t l_value[72] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VPD_DQ_MAP, i_target, l_value) );
memcpy(o_array, &l_value, 72);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_VPD_DQ_MAP: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC0F - Command Latency Adder Control Word; Default value - 04. Values
/// Range from 00 to 04. No need to calculate; User can override with desired experimental
/// value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0F, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0F: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC0F - Command Latency Adder Control Word; Default value - 04. Values
/// Range from 00 to 04. No need to calculate; User can override with desired experimental
/// value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0F, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0F: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_CS_CMD_LATENCY getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg.
/// Each memory channel will have a value.
///
inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CS_CMD_LATENCY, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_CS_CMD_LATENCY: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_CS_CMD_LATENCY getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg.
/// Each memory channel will have a value.
///
inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CS_CMD_LATENCY, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_CS_CMD_LATENCY: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_CA_PARITY_LATENCY getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg.
/// Each memory channel will have a value.
///
inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CA_PARITY_LATENCY, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_CA_PARITY_LATENCY: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_CA_PARITY_LATENCY getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg.
/// Each memory channel will have a value.
///
inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CA_PARITY_LATENCY, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_CA_PARITY_LATENCY: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC02 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range
/// from 0-8. No need to calculate; User can override with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC02, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC02: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC02 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range
/// from 0-8. No need to calculate; User can override with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC02, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC02: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC03 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default
/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from
/// SPD byte 137, 1st Nibble for CS and CA.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC03, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC03: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC03 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default
/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from
/// SPD byte 137, 1st Nibble for CS and CA.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC03, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC03: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC04 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default
/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from
/// SPD byte 137, 2nd Nibble for ODT and CKE.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC04, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC04: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC04 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default
/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from
/// SPD byte 137, 2nd Nibble for ODT and CKE.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC04, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC04: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC05 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC05 - Clock Driver Characteristics Control Word; Default value -
/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD
/// byte 138, 2nd Nibble for CK.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC05, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC05: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC05 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC05 - Clock Driver Characteristics Control Word; Default value -
/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD
/// byte 138, 2nd Nibble for CK.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC05, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC05: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC0B getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR.
/// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User
/// can override with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0B, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0B: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC0B getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR.
/// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User
/// can override with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0B, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0B: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC1X getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range
/// from 00 to 3F. No need to calculate; User can override with desired experimental
/// value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC1X, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC1X: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC1X getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range
/// from 00 to 3F. No need to calculate; User can override with desired experimental
/// value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC1X, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC1X: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC7X getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to
/// FF.No need to calculate. User can override with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC7X, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC7X: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F0RC7X getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to
/// FF.No need to calculate. User can override with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC7X, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC7X: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC00 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC00, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC00: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC00 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC00, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC00: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC02 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default
/// value - 00. Values Range from 00 to 0F. No need to calculate; User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC02, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC02: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC02 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default
/// value - 00. Values Range from 00 to 0F. No need to calculate; User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc02(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC02, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC02: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC03 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC03, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC03: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC03 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc03(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC03, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC03: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC04 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC04, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC04: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC04 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc04(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC04, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC04: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC05 getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
uint8_t l_value[2] = {};
const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>();
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC05, l_port, l_value) );
o_value = l_value[mss::index(i_target)];
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC05: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_DIMM_DDR4_F1RC05 getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t&[] array reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default
/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override
/// with desired experimental value.
///
inline fapi2::ReturnCode get_dimm_ddr4_f1rc05(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2])
{
uint8_t l_value[2] = {};
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC05, i_target, l_value) );
memcpy(o_array, &l_value, 2);
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC05: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_REORDER_QUEUE_SETTING getter
/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Contains the settings for write/read reorder queue
///
inline fapi2::ReturnCode get_reorder_queue_setting(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
uint8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_REORDER_QUEUE_SETTING, i_target, o_value) );
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_REORDER_QUEUE_SETTING: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MEM_2N_MODE getter
/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_mc_port_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Default value for 2N Mode from Signal Integrity. 0x0 = Invalid Mode, 0x01 = 1N Mode
/// , 0x02 = 2N Mode If value is set to 0x0 this indicate value was never initialized
/// correctly.
///
inline fapi2::ReturnCode get_mem_2n_mode(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, uint8_t& o_value)
{
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_2N_MODE, i_target, o_value) );
return fapi2::current_err;
fapi_try_exit:
FAPI_ERR("failed getting ATTR_MEM_2N_MODE: 0x%lx (target: %s)",
uint64_t(fapi2::current_err), mss::c_str(i_target));
return fapi2::current_err;
}
///
/// @brief ATTR_MSS_OMI_EDPL_DISABLE getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generate_other_attr_params
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note EDPL (Error Detection Per Lane) is a feature in the DL that adds some additional
/// checks to the traffic going across the OpenCAPI link in order to better track which
/// lanes are having issues. Note: EDPL must be set the same on both sides of the link.
/// This attribute affects both the proc/mc side and the OCMB side.
///
inline fapi2::ReturnCode get_mss_omi_edpl_disable(uint8_t& o_value)
{