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hwas.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/usr/hwas/common/hwas.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2012,2017 */
/* [+] Google Inc. */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
/**
* @file hwas.C
*
* HardWare Availability Service functions.
* See hwas.H for doxygen documentation tags.
*
*/
/******************************************************************************/
// Includes
/******************************************************************************/
#include <stdint.h>
#include <algorithm>
#ifdef __HOSTBOOT_MODULE
#include <config.h>
#endif
#include <targeting/common/commontargeting.H>
#include <targeting/common/utilFilter.H>
#include <hwas/common/hwas.H>
#include <hwas/common/hwasCommon.H>
#include <hwas/common/hwasError.H>
#include <hwas/common/deconfigGard.H>
#include <hwas/common/hwas_reasoncodes.H>
#include <targeting/common/utilFilter.H>
namespace HWAS
{
using namespace TARGETING;
using namespace HWAS::COMMON;
// trace setup; used by HWAS_DBG and HWAS_ERR macros
HWAS_TD_t g_trac_dbg_hwas = NULL; // debug - fast
HWAS_TD_t g_trac_imp_hwas = NULL; // important - slow
#ifdef __HOSTBOOT_MODULE
TRAC_INIT(&g_trac_dbg_hwas, "HWAS", KILOBYTE );
TRAC_INIT(&g_trac_imp_hwas, "HWAS_I", KILOBYTE );
#else
TRAC_INIT(&g_trac_dbg_hwas, "HWAS", 1024 );
TRAC_INIT(&g_trac_imp_hwas, "HWAS_I", 1024 );
#endif
// SORT functions that we'll use for PR keyword processing
bool compareProcGroup(procRestrict_t t1, procRestrict_t t2)
{
if (t1.group == t2.group)
{
return (t1.target->getAttr<ATTR_HUID>() <
t2.target->getAttr<ATTR_HUID>());
}
return (t1.group < t2.group);
}
bool compareAffinity(const TargetInfo t1, const TargetInfo t2)
{
return t1.affinityPath < t2.affinityPath;
}
/**
* @brief simple helper fn to get and set hwas state to poweredOn,
* present, functional
*
* @param[in] i_target pointer to target that we're looking at
* @param[in] i_present boolean indicating present or not
* @param[in] i_functional boolean indicating functional or not
* @param[in] i_errlEid erreid that caused change to non-funcational;
* 0 if not associated with an error or if
* functional is true
*
* @return none
*
*/
void enableHwasState(Target *i_target,
bool i_present, bool i_functional,
uint32_t i_errlEid)
{
HwasState hwasState = i_target->getAttr<ATTR_HWAS_STATE>();
if (i_functional == false)
{ // record the EID as a reason that we're marking non-functional
hwasState.deconfiguredByEid = i_errlEid;
}
hwasState.poweredOn = true;
hwasState.present = i_present;
hwasState.functional = i_functional;
i_target->setAttr<ATTR_HWAS_STATE>( hwasState );
}
/**
* @brief simple helper fn to check L3/L2/REFR triplets in PG EPx data
*
* @param[in] i_pgData EPx data from PG keyword VPD
*
* @return bool triplets are valid
*
*/
bool areL3L2REFRtripletsValid(uint16_t i_pgData)
{
bool l_valid = true;
// Check that triplets are valid, that is, all good or all bad
for (uint8_t l_triplet = 0;
l_triplet <= 1;
l_triplet++)
{
// Check if all are good in the triplet
if ((i_pgData & VPD_CP00_PG_EPx_L3L2REFR[l_triplet]) == 0)
{
continue;
}
// Check if all are bad in the triplet
if ((i_pgData & VPD_CP00_PG_EPx_L3L2REFR[l_triplet]) ==
VPD_CP00_PG_EPx_L3L2REFR[l_triplet])
{
continue;
}
l_valid = false;
break;
}
return l_valid;
}
/**
* @brief simple helper fn to check core data for rollup
*
* @param[in] i_firstCore First core to look at
* @param[in] i_numCoresToCheck number of cores to check from first one
* @param[in] i_pgData PG keyword VPD
*
* @return bool All ECxx domains were marked bad
*
*/
bool allCoresBad(const uint8_t & i_firstCore,
const uint8_t & i_numCoresToCheck,
const uint16_t i_pgData[])
{
bool coresBad = true;
uint8_t coreNum = 0;
do
{
// don't look outside of EC core entries
if ((i_firstCore + coreNum) >= VPD_CP00_PG_ECxx_MAX_ENTRIES)
{
HWAS_INF("allCoresBad: requested %d cores beginning at %d, "
"but only able to check %d cores",
i_numCoresToCheck, i_firstCore, coreNum);
break;
}
if (i_pgData[VPD_CP00_PG_EC00_INDEX + i_firstCore + coreNum] ==
VPD_CP00_PG_ECxx_GOOD)
{
coresBad = false;
}
coreNum++;
}
while (coresBad && (coreNum < i_numCoresToCheck));
return coresBad;
}
errlHndl_t discoverTargets()
{
HWAS_DBG("discoverTargets entry");
errlHndl_t errl = NULL;
// loop through all the targets and set HWAS_STATE to a known default
for (TargetIterator target = targetService().begin();
target != targetService().end();
++target)
{
// TODO:RTC:151617 Need to find a better way
// to initialize the target
if((target->getAttr<ATTR_TYPE>() == TYPE_SP) ||
(target->getAttr<ATTR_TYPE>() == TYPE_BMC))
{
HwasState hwasState = target->getAttr<ATTR_HWAS_STATE>();
hwasState.deconfiguredByEid = 0;
hwasState.poweredOn = true;
hwasState.present = true;
hwasState.functional = true;
hwasState.dumpfunctional = false;
target->setAttr<ATTR_HWAS_STATE>(hwasState);
}else
{
HwasState hwasState = target->getAttr<ATTR_HWAS_STATE>();
hwasState.deconfiguredByEid = 0;
hwasState.poweredOn = false;
hwasState.present = false;
hwasState.functional = false;
hwasState.dumpfunctional = false;
target->setAttr<ATTR_HWAS_STATE>(hwasState);
}
}
// Assumptions and actions:
// CLASS_SYS (exactly 1) - mark as present
// CLASS_ENC, TYPE_PROC, TYPE_MCS, TYPE_MEMBUF, TYPE_DIMM
// (ALL require hardware query) - call platPresenceDetect
// \->children: CLASS_* (NONE require hardware query) - mark as present
do
{
// find CLASS_SYS (the top level target)
Target* pSys;
targetService().getTopLevelTarget(pSys);
HWAS_ASSERT(pSys,
"HWAS discoverTargets: no CLASS_SYS TopLevelTarget found");
// mark this as present
enableHwasState(pSys, true, true, 0);
HWAS_DBG("pSys %.8X - marked present",
pSys->getAttr<ATTR_HUID>());
// find list of all we need to call platPresenceDetect against
PredicateCTM predEnc(CLASS_ENC);
PredicateCTM predChip(CLASS_CHIP);
PredicateCTM predDimm(CLASS_LOGICAL_CARD, TYPE_DIMM);
PredicateCTM predMcs(CLASS_UNIT, TYPE_MCS);
PredicatePostfixExpr checkExpr;
checkExpr.push(&predChip).push(&predDimm).Or().push(&predEnc).Or().
push(&predMcs).Or();
TargetHandleList pCheckPres;
targetService().getAssociated( pCheckPres, pSys,
TargetService::CHILD, TargetService::ALL, &checkExpr );
// pass this list to the hwas platform-specific api where
// pCheckPres will be modified to only have present targets
HWAS_DBG("pCheckPres size: %d", pCheckPres.size());
errl = platPresenceDetect(pCheckPres);
HWAS_DBG("pCheckPres size: %d", pCheckPres.size());
if (errl != NULL)
{
break; // break out of the do/while so that we can return
}
// for each, read their ID/EC level. if that works,
// mark them and their descendants as present
// read the partialGood vector to determine if any are not functional
// and read and store values from the PR keyword
// list of procs and data that we'll need to look at when potentially
// reducing the list of valid ECs later
procRestrict_t l_procEntry;
std::vector <procRestrict_t> l_procRestrictList;
// sort the list by ATTR_HUID to ensure that we
// start at the same place each time
std::sort(pCheckPres.begin(), pCheckPres.end(),
compareTargetHuid);
for (TargetHandleList::const_iterator pTarget_it = pCheckPres.begin();
pTarget_it != pCheckPres.end();
++pTarget_it
)
{
TargetHandle_t pTarget = *pTarget_it;
// if CLASS_ENC is still in this list, mark as present
if (pTarget->getAttr<ATTR_CLASS>() == CLASS_ENC)
{
enableHwasState(pTarget, true, true, 0);
HWAS_DBG("pTarget %.8X - CLASS_ENC marked present",
pTarget->getAttr<ATTR_HUID>());
// on to the next target
continue;
}
bool chipPresent = true;
bool chipFunctional = true;
uint32_t errlEid = 0;
uint16_t pgData[VPD_CP00_PG_DATA_LENGTH / sizeof(uint16_t)];
bzero(pgData, sizeof(pgData));
if( (pTarget->getAttr<ATTR_CLASS>() == CLASS_CHIP) &&
(pTarget->getAttr<ATTR_TYPE>() != TYPE_TPM) &&
(pTarget->getAttr<ATTR_TYPE>() != TYPE_SP) )
{
// read Chip ID/EC data from these physical chips
errl = platReadIDEC(pTarget);
if (errl)
{ // read of ID/EC failed even tho we THOUGHT we were present.
HWAS_INF("pTarget %.8X - read IDEC failed (eid 0x%X) - bad",
errl->eid(), pTarget->getAttr<ATTR_HUID>());
// chip NOT present and NOT functional, so that FSP doesn't
// include this for HB to process
chipPresent = false;
chipFunctional = false;
errlEid = errl->eid();
// commit the error but keep going
errlCommit(errl, HWAS_COMP_ID);
// errl is now NULL
}
else if (pTarget->getAttr<ATTR_TYPE>() == TYPE_PROC)
{
// read partialGood vector from these as well.
errl = platReadPartialGood(pTarget, pgData);
if (errl)
{ // read of PG failed even tho we were present..
HWAS_INF("pTarget %.8X - read PG failed (eid 0x%X)- bad",
errl->eid(), pTarget->getAttr<ATTR_HUID>());
chipFunctional = false;
errlEid = errl->eid();
// commit the error but keep going
errlCommit(errl, HWAS_COMP_ID);
// errl is now NULL
}
else
{
// look at the 'nest' logic to override the
// functionality of this proc
chipFunctional = isChipFunctional(pTarget, pgData);
// Fill in a dummy restrict list
l_procEntry.target = pTarget;
// every proc is uniquely counted
l_procEntry.group = pTarget->getAttr<ATTR_HUID>();
// just 1 proc per group
l_procEntry.procs = 1;
// indicates we should use all available ECs
l_procEntry.maxECs = UINT32_MAX;
l_procRestrictList.push_back(l_procEntry);
}
} // TYPE_PROC
} // CLASS_CHIP
HWAS_DBG("pTarget %.8X - detected present, %sfunctional",
pTarget->getAttr<ATTR_HUID>(),
chipFunctional ? "" : "NOT ");
// now need to mark all of this target's
// physical descendants as present and functional as appropriate
TargetHandleList pDescList;
targetService().getAssociated( pDescList, pTarget,
TargetService::CHILD, TargetService::ALL);
for (TargetHandleList::const_iterator pDesc_it = pDescList.begin();
pDesc_it != pDescList.end();
++pDesc_it)
{
TargetHandle_t pDesc = *pDesc_it;
// by default, the descendant's functionality is 'inherited'
bool descFunctional = chipFunctional;
if (chipFunctional)
{ // if the chip is functional, then look through the
// partialGood vector to see if its chiplets
// are functional
descFunctional = isDescFunctional(pDesc, pgData);
}
if (pDesc->getAttr<ATTR_TYPE>() == TYPE_PERV)
{
// for sub-parts of PERV, it's always present.
enableHwasState(pDesc, chipFunctional, descFunctional,
errlEid);
HWAS_DBG("pDesc %.8X - marked %spresent, %sfunctional",
pDesc->getAttr<ATTR_HUID>(),
"",
descFunctional ? "" : "NOT ");
}
else
{
// for other sub-parts, if it's not functional,
// it's not present.
enableHwasState(pDesc, descFunctional, descFunctional,
errlEid);
HWAS_DBG("pDesc %.8X - marked %spresent, %sfunctional",
pDesc->getAttr<ATTR_HUID>(),
descFunctional ? "" : "NOT ",
descFunctional ? "" : "NOT ");
}
}
// set HWAS state to show CHIP is present, functional per above
enableHwasState(pTarget, chipPresent, chipFunctional, errlEid);
} // for pTarget_it
// Check for non-present Procs and if found, trigger
// DeconfigGard::_invokeDeconfigureAssocProc() to run by setting
// setXAOBusEndpointDeconfigured to true
PredicateCTM predProc(CLASS_CHIP, TYPE_PROC);
TargetHandleList l_procs;
targetService().getAssociated(l_procs,
pSys,
TargetService::CHILD,
TargetService::ALL,
&predProc);
for (TargetHandleList::const_iterator
l_procsIter = l_procs.begin();
l_procsIter != l_procs.end();
++l_procsIter)
{
if ( !(*l_procsIter)->getAttr<ATTR_HWAS_STATE>().present )
{
HWAS_INF("discoverTargets: Proc %.8X not present",
(*l_procsIter)->getAttr<ATTR_HUID>());
HWAS::theDeconfigGard().setXAOBusEndpointDeconfigured(true);
}
}
//Now that all proc's are created and functional, we need to
//calculate the system EFFECTIVE_EC
calculateEffectiveEC();
// Potentially reduce the number of ec/core units that are present
// based on fused mode
// marking bad units as present=false;
// deconfigReason = 0 because present is false so this is not a
// deconfigured event.
errl = restrictECunits(l_procRestrictList, false, 0);
if (errl)
{
HWAS_ERR("discoverTargets: restrictECunits failed");
break;
}
// Mark any MCA units that are present but have a disabled port
// as non-functional
errl = markDisabledMcas();
if (errl)
{
HWAS_ERR("discoverTargets: markDisabledMcas failed");
break;
}
// call invokePresentByAssoc() to obtain functional MCSs, MEMBUFs, and
// DIMMs for non-direct memory or MCSs, MCAs, and DIMMs for direct
// memory. Call algorithm function presentByAssoc() to determine
// targets that need to be deconfigured
invokePresentByAssoc();
} while (0);
if (errl)
{
HWAS_INF("discoverTargets failed (plid 0x%X)", errl->plid());
}
else
{
HWAS_INF("discoverTargets completed successfully");
}
return errl;
} // discoverTargets
bool isChipFunctional(const TARGETING::TargetHandle_t &i_target,
const uint16_t i_pgData[])
{
bool l_chipFunctional = true;
ATTR_MODEL_type l_model = i_target->getAttr<ATTR_MODEL>();
uint16_t l_xbus = (l_model == MODEL_NIMBUS) ?
VPD_CP00_PG_XBUS_GOOD_NIMBUS : VPD_CP00_PG_XBUS_GOOD_CUMULUS;
// Check all bits in FSI entry
if (i_pgData[VPD_CP00_PG_FSI_INDEX] !=
VPD_CP00_PG_FSI_GOOD)
{
HWAS_INF("pTarget %.8X - FSI pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_FSI_INDEX,
i_pgData[VPD_CP00_PG_FSI_INDEX],
VPD_CP00_PG_FSI_GOOD);
l_chipFunctional = false;
}
else
// Check all bits in PRV entry
if (i_pgData[VPD_CP00_PG_PERVASIVE_INDEX] !=
VPD_CP00_PG_PERVASIVE_GOOD)
{
HWAS_INF("pTarget %.8X - Pervasive pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_PERVASIVE_INDEX,
i_pgData[VPD_CP00_PG_PERVASIVE_INDEX],
VPD_CP00_PG_PERVASIVE_GOOD);
l_chipFunctional = false;
}
else
// Check all bits in N0 entry
if (i_pgData[VPD_CP00_PG_N0_INDEX] != VPD_CP00_PG_N0_GOOD)
{
HWAS_INF("pTarget %.8X - N0 pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_N0_INDEX,
i_pgData[VPD_CP00_PG_N0_INDEX],
VPD_CP00_PG_N0_GOOD);
l_chipFunctional = false;
}
else
// Check bits in N1 entry except those in partial good region
if ((i_pgData[VPD_CP00_PG_N1_INDEX] &
~VPD_CP00_PG_N1_PG_MASK) != VPD_CP00_PG_N1_GOOD)
{
HWAS_INF("pTarget %.8X - N1 pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_N1_INDEX,
i_pgData[VPD_CP00_PG_N1_INDEX],
VPD_CP00_PG_N1_GOOD);
l_chipFunctional = false;
}
else
// Check all bits in N2 entry
if (i_pgData[VPD_CP00_PG_N2_INDEX] != VPD_CP00_PG_N2_GOOD)
{
HWAS_INF("pTarget %.8X - N2 pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_N2_INDEX,
i_pgData[VPD_CP00_PG_N2_INDEX],
VPD_CP00_PG_N2_GOOD);
l_chipFunctional = false;
}
else
// Check bits in N3 entry except those in partial good region
if ((i_pgData[VPD_CP00_PG_N3_INDEX] &
~VPD_CP00_PG_N3_PG_MASK) != VPD_CP00_PG_N3_GOOD)
{
HWAS_INF("pTarget %.8X - N3 pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_N3_INDEX,
i_pgData[VPD_CP00_PG_N3_INDEX],
VPD_CP00_PG_N3_GOOD);
l_chipFunctional = false;
}
else
// Check bits in XBUS entry, ignoring individual xbus targets
// Note that what is good is different bewteen Nimbus/Cumulus
if (((i_pgData[VPD_CP00_PG_XBUS_INDEX] &
~VPD_CP00_PG_XBUS_PG_MASK) != l_xbus))
{
HWAS_INF("pTarget %.8X - XBUS pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_XBUS_INDEX,
i_pgData[VPD_CP00_PG_XBUS_INDEX],
l_xbus);
l_chipFunctional = false;
}
return l_chipFunctional;
} // isChipFunctional
bool isDescFunctional(const TARGETING::TargetHandle_t &i_desc,
const uint16_t i_pgData[])
{
bool l_descFunctional = true;
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_XBUS)
{
ATTR_CHIP_UNIT_type indexXB =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// Check bits in XBUS entry
if ((i_pgData[VPD_CP00_PG_XBUS_INDEX] &
VPD_CP00_PG_XBUS_IOX[indexXB]) != 0)
{
HWAS_INF("pDesc %.8X - XBUS%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexXB,
VPD_CP00_PG_XBUS_INDEX,
i_pgData[VPD_CP00_PG_XBUS_INDEX],
(i_pgData[VPD_CP00_PG_XBUS_INDEX] &
~VPD_CP00_PG_XBUS_IOX[indexXB]));
l_descFunctional = false;
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_OBUS)
{
ATTR_CHIP_UNIT_type indexOB =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// Check all bits in OBUSx entry
if (i_pgData[VPD_CP00_PG_OB0_INDEX + indexOB] !=
VPD_CP00_PG_OBUS_GOOD)
{
HWAS_INF("pDesc %.8X - OB%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexOB,
VPD_CP00_PG_OB0_INDEX + indexOB,
i_pgData[VPD_CP00_PG_OB0_INDEX + indexOB],
VPD_CP00_PG_OBUS_GOOD);
l_descFunctional = false;
}
else
// Check PBIOO0 bit in N1 entry
// @TODO RTC:134608 PBIOO0 seems to be good with Nimbus and Cumulus
// except Nimbus Sforza (without optics and NVLINK)
// so is it associated with all OBUS entries or just
// with OBUS0 and OBUS3 -- verify this
if ((i_pgData[VPD_CP00_PG_N1_INDEX] &
VPD_CP00_PG_N1_PBIOO0) != 0)
{
HWAS_INF("pDesc %.8X - OB%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexOB,
VPD_CP00_PG_N1_INDEX,
i_pgData[VPD_CP00_PG_N1_INDEX],
(i_pgData[VPD_CP00_PG_N1_INDEX] &
~VPD_CP00_PG_N1_PBIOO0));
l_descFunctional = false;
}
else
// Check PBIOO1 bit in N1 entry if second or third OBUS
// @TODO RTC:134608 PBIOO1 seems to be associated with OBUS1 and OBUS2
// which only are valid on a Cumulus -- verify this
if (((1 == indexOB) || (2 == indexOB)) &&
((i_pgData[VPD_CP00_PG_N1_INDEX] &
VPD_CP00_PG_N1_PBIOO1) != 0))
{
HWAS_INF("pDesc %.8X - OB%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexOB,
VPD_CP00_PG_N1_INDEX,
i_pgData[VPD_CP00_PG_N1_INDEX],
(i_pgData[VPD_CP00_PG_N1_INDEX] &
~VPD_CP00_PG_N1_PBIOO1));
l_descFunctional = false;
}
}
else
if ((i_desc->getAttr<ATTR_TYPE>() == TYPE_PEC)
|| (i_desc->getAttr<ATTR_TYPE>() == TYPE_PHB))
{
Target * l_targ = NULL;
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_PHB)
{
//First get Parent PEC target as there are no PG bits for PHB
TargetHandleList pParentPECList;
getParentAffinityTargetsByState(pParentPECList, i_desc,
CLASS_UNIT, TYPE_PEC, UTIL_FILTER_ALL);
HWAS_ASSERT((pParentPECList.size() == 1),
"isDescFunctional(): pParentPECList != 1");
l_targ = pParentPECList[0];
}
else
{
l_targ = const_cast<TARGETING::Target*>(i_desc);
}
ATTR_CHIP_UNIT_type indexPCI =
l_targ->getAttr<ATTR_CHIP_UNIT>();
// Check all bits in PCIx entry
if (i_pgData[VPD_CP00_PG_PCI0_INDEX + indexPCI] !=
VPD_CP00_PG_PCIx_GOOD[indexPCI])
{
HWAS_INF("pDesc %.8X - PCI%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexPCI,
VPD_CP00_PG_PCI0_INDEX + indexPCI,
i_pgData[VPD_CP00_PG_PCI0_INDEX + indexPCI],
VPD_CP00_PG_PCIx_GOOD[indexPCI]);
l_descFunctional = false;
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_EQ)
{
ATTR_CHIP_UNIT_type indexEP =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// Check bits in EPx entry, validating triplets in partial good region
if (((i_pgData[VPD_CP00_PG_EP0_INDEX + indexEP]
& ~VPD_CP00_PG_EPx_PG_MASK) !=
VPD_CP00_PG_EPx_GOOD) ||
(!areL3L2REFRtripletsValid(i_pgData[VPD_CP00_PG_EP0_INDEX +
indexEP])))
{
HWAS_INF("pDesc %.8X - EQ%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexEP,
VPD_CP00_PG_EP0_INDEX + indexEP,
i_pgData[VPD_CP00_PG_EP0_INDEX + indexEP],
VPD_CP00_PG_EPx_GOOD);
l_descFunctional = false;
}
else
{
// Look for a rollup bad status
// Either both EXs are bad or all 4 EC's are bad
// index of first EX of 2 EXs under this EQ
uint8_t indexEX = (uint8_t)indexEP * 2;
// index of first EC of 4 ECs under this EQ
uint8_t indexEC = indexEX * 2;
uint8_t coresToCheck = 4;
// check if both EX's are bad
if (((i_pgData[VPD_CP00_PG_EP0_INDEX + indexEP] &
VPD_CP00_PG_EPx_L3L2REFR[0]) != 0) &&
((i_pgData[VPD_CP00_PG_EP0_INDEX + indexEP] &
VPD_CP00_PG_EPx_L3L2REFR[1]) != 0))
{
HWAS_INF("pDesc %.8X - EQ%d marked bad because its EXs "
"(%d and %d) are both bad",
i_desc->getAttr<ATTR_HUID>(),
indexEP,
indexEX, indexEX+1);
l_descFunctional = false;
}
else
// check if child cores are bad
if (allCoresBad(indexEC, coresToCheck, i_pgData))
{
HWAS_INF("pDesc %.8X - EQ%d marked bad because its %d CORES "
"(EC%d - EC%d) are all bad",
i_desc->getAttr<ATTR_HUID>(),
indexEP,
coresToCheck, indexEC, indexEC+3);
l_descFunctional = false;
}
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_EX)
{
ATTR_CHIP_UNIT_type indexEX =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// 2 EX chiplets per EP/EQ chiplet
size_t indexEP = indexEX / 2;
// 2 L3/L2/REFR triplets per EX chiplet
size_t indexL3L2REFR = indexEX % 2;
// 2 EC children per EX
uint8_t indexEC = indexEX * 2;
uint8_t allCoresToCheck = 2; // 2 CORES per EX
// Check triplet of bits in EPx entry
if ((i_pgData[VPD_CP00_PG_EP0_INDEX + indexEP] &
VPD_CP00_PG_EPx_L3L2REFR[indexL3L2REFR]) != 0)
{
HWAS_INF("pDesc %.8X - EX%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexEX,
VPD_CP00_PG_EP0_INDEX + indexEP,
i_pgData[VPD_CP00_PG_EP0_INDEX + indexEP],
(i_pgData[VPD_CP00_PG_EP0_INDEX + indexEP] &
~VPD_CP00_PG_EPx_L3L2REFR[indexL3L2REFR]));
l_descFunctional = false;
}
else
// Check that EX does not have 2 bad CORE children
if (allCoresBad(indexEC, allCoresToCheck, i_pgData))
{
HWAS_INF("pDesc %.8X - EX%d marked bad since it has no good cores",
i_desc->getAttr<ATTR_HUID>(), indexEX);
HWAS_INF("(core %d: actual 0x%04X, expected 0x%04X) "
"(core %d: actual 0x%04X, expected 0x%04X)",
indexEC, i_pgData[VPD_CP00_PG_EC00_INDEX + indexEC],
VPD_CP00_PG_ECxx_GOOD,
indexEC+1, i_pgData[VPD_CP00_PG_EC00_INDEX + indexEC+1],
VPD_CP00_PG_ECxx_GOOD);
l_descFunctional = false;
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_CORE)
{
ATTR_CHIP_UNIT_type indexEC =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// Check all bits in ECxx entry
if (i_pgData[VPD_CP00_PG_EC00_INDEX + indexEC] !=
VPD_CP00_PG_ECxx_GOOD)
{
HWAS_INF("pDesc %.8X - CORE/EC%2.2d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexEC,
VPD_CP00_PG_EC00_INDEX + indexEC,
i_pgData[VPD_CP00_PG_EC00_INDEX + indexEC],
VPD_CP00_PG_ECxx_GOOD);
l_descFunctional = false;
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_MCBIST)
{
ATTR_CHIP_UNIT_type indexMCBIST =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// 2 MCS chiplets per MCBIST / MCU
size_t indexMCS = indexMCBIST * 2;
// Check MCS01 bit in N3 entry if first MCBIST / MCU
if ((0 == indexMCBIST) &&
((i_pgData[VPD_CP00_PG_N3_INDEX] &
VPD_CP00_PG_N3_MCS01) != 0))
{
HWAS_INF("pDesc %.8X - MCBIST%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexMCBIST,
VPD_CP00_PG_N3_INDEX,
i_pgData[VPD_CP00_PG_N3_INDEX],
(i_pgData[VPD_CP00_PG_N3_INDEX] &
~VPD_CP00_PG_N3_MCS01));
l_descFunctional = false;
}
else
// Check MCS23 bit in N1 entry if second MCBIST / MCU
if ((1 == indexMCBIST) &&
((i_pgData[VPD_CP00_PG_N1_INDEX] &
VPD_CP00_PG_N1_MCS23) != 0))
{
HWAS_INF("pDesc %.8X - MCBIST%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexMCBIST,
VPD_CP00_PG_N1_INDEX,
i_pgData[VPD_CP00_PG_N1_INDEX],
(i_pgData[VPD_CP00_PG_N1_INDEX] &
~VPD_CP00_PG_N1_MCS23));
l_descFunctional = false;
}
else
// Check bits in MCxx entry except those in partial good region
if ((i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]]
& ~VPD_CP00_PG_MCxx_PG_MASK) !=
VPD_CP00_PG_MCxx_GOOD)
{
HWAS_INF("pDesc %.8X - MCBIST%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexMCBIST,
VPD_CP00_PG_MCxx_INDEX[indexMCS],
i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]],
VPD_CP00_PG_MCxx_GOOD);
l_descFunctional = false;
}
else
// One MCA (the first one = mca0 or mca4) on each MC must be functional
// for zqcal to work on any of the MCAs on that side
if ( (i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]] &
VPD_CP00_PG_MCA_MAGIC_PORT_MASK) != 0 )
{
HWAS_INF("pDesc %.8X - MCBIST%d pgData[%d]: "
"0x%04X marked bad because of bad magic MCA port (0x%04X)",
i_desc->getAttr<ATTR_HUID>(), indexMCBIST,
VPD_CP00_PG_MCxx_INDEX[indexMCS],
i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]],
VPD_CP00_PG_MCA_MAGIC_PORT_MASK);
l_descFunctional = false;
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_MCS)
{
ATTR_CHIP_UNIT_type indexMCS =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// Check MCS01 bit in N3 entry if first or second MCS
if (((0 == indexMCS) || (1 == indexMCS)) &&
((i_pgData[VPD_CP00_PG_N3_INDEX] &
VPD_CP00_PG_N3_MCS01) != 0))
{
HWAS_INF("pDesc %.8X - MCS%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexMCS,
VPD_CP00_PG_N3_INDEX,
i_pgData[VPD_CP00_PG_N3_INDEX],
(i_pgData[VPD_CP00_PG_N3_INDEX] &
~VPD_CP00_PG_N3_MCS01));
l_descFunctional = false;
}
else
// Check MCS23 bit in N1 entry if third or fourth MCS
if (((2 == indexMCS) || (3 == indexMCS)) &&
((i_pgData[VPD_CP00_PG_N1_INDEX] &
VPD_CP00_PG_N1_MCS23) != 0))
{
HWAS_INF("pDesc %.8X - MCS%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexMCS,
VPD_CP00_PG_N1_INDEX,
i_pgData[VPD_CP00_PG_N1_INDEX],
(i_pgData[VPD_CP00_PG_N1_INDEX] &
~VPD_CP00_PG_N1_MCS23));
l_descFunctional = false;
}
else
// Check bits in MCxx entry including specific IOM bit,
// but not other bits in partial good region
if ((i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]]
& ~(VPD_CP00_PG_MCxx_PG_MASK
& ~VPD_CP00_PG_MCxx_IOMyy[indexMCS])) !=
VPD_CP00_PG_MCxx_GOOD)
{
HWAS_INF("pDesc %.8X - MCS%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexMCS,
VPD_CP00_PG_MCxx_INDEX[indexMCS],
i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]],
(i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]] &
~VPD_CP00_PG_MCxx_IOMyy[indexMCS]));
l_descFunctional = false;
}
else
// One MCA (the first one = mca0 or mca4) on each MC must be functional
// for zqcal to work on any of the MCAs on that side
if ( (i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]] &
VPD_CP00_PG_MCA_MAGIC_PORT_MASK) != 0 )
{
HWAS_INF("pDesc %.8X - MCS%d pgData[%d]: "
"0x%04X marked bad because of bad magic MCA port (0x%04X)",
i_desc->getAttr<ATTR_HUID>(), indexMCS,
VPD_CP00_PG_MCxx_INDEX[indexMCS],
i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]],
VPD_CP00_PG_MCA_MAGIC_PORT_MASK);
l_descFunctional = false;
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_MCA)
{
ATTR_CHIP_UNIT_type indexMCA =
i_desc->getAttr<ATTR_CHIP_UNIT>();
// 2 MCA chiplets per MCS
size_t indexMCS = indexMCA / 2;
// Check IOM bit in MCxx entry
if ((i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]]
& VPD_CP00_PG_MCxx_IOMyy[indexMCS]) != 0)
{
HWAS_INF("pDesc %.8X - MCA%d pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(), indexMCA,
VPD_CP00_PG_MCxx_INDEX[indexMCS],
i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]],
(i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]] &
~VPD_CP00_PG_MCxx_IOMyy[indexMCS]));
l_descFunctional = false;
}
else
// One MCA (the first one = mca0 or mca4) on each MC must be functional
// for zqcal to work on any of the MCAs on that side
if ( (i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]] &
VPD_CP00_PG_MCA_MAGIC_PORT_MASK) != 0 )
{
HWAS_INF("pDesc %.8X - MCA%d pgData[%d]: "
"0x%04X marked bad because of bad magic MCA port (0x%04X)",
i_desc->getAttr<ATTR_HUID>(), indexMCA,
VPD_CP00_PG_MCxx_INDEX[indexMCS],
i_pgData[VPD_CP00_PG_MCxx_INDEX[indexMCS]],
VPD_CP00_PG_MCA_MAGIC_PORT_MASK);
l_descFunctional = false;
}
}
else
if (i_desc->getAttr<ATTR_TYPE>() == TYPE_OBUS_BRICK)
{
//If NPU is bad and Bricks are non-SMP, then mark them bad
if ((i_desc->getAttr<ATTR_OPTICS_CONFIG_MODE>()
!= OPTICS_CONFIG_MODE_SMP) &&
((i_pgData[VPD_CP00_PG_N3_INDEX] & VPD_CP00_PG_N3_NPU) != 0))
{
HWAS_INF("pDesc %.8X - OBUS_BRICK pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_desc->getAttr<ATTR_HUID>(),