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Multiple fixes to enable p9c draminit_training_adv during IPL
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 Increase poll limit for PDA operations on p9c to fix CCS hangs
 Reduce repetitive access to ATTR_CEN_VPD_ODT_WR in PDA code
 Reduce repetitive access to ATTR_CEN_VPD_ISDIMMTOC4DQ/S in generic_shmoo
 Reduce repetitive access to ATTR_BAD_DQ_BITMAP in generic_shmoo

Change-Id: Ibe130c590bbb5b50a7c31fa0b0add4c891c4505a
CQ:SW446241
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65190
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65292
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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@stermole @crgeddes
stermole authored and crgeddes committed Sep 26, 2018
1 parent 272a724 commit 0101df3
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Showing 10 changed files with 195 additions and 74 deletions.
29 changes: 26 additions & 3 deletions src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C
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Original file line number Diff line number Diff line change
Expand Up @@ -1915,13 +1915,17 @@ extern "C" {
///@param[in] i_input_index_u8=0-79/0-71/0-8/0-19
///@param[in] i_verbose-extra print statements
///@param[out] C4 bit=o_value
///@param[in] i_isdm_c4_dq optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQ and skip attr access (default = nullptr)
///@param[in] i_isdm_c4_dqs optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQS and skip attr access (default = nullptr)
///@return fapi2::returnCode
fapi2::ReturnCode rosetta_map(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba,
const uint8_t i_port,
const input_type i_input_type_e,
const uint8_t i_input_index,
const bool i_verbose,
uint8_t& o_value) //This function is used by some other procedures
uint8_t& o_value,
uint8_t i_isdm_c4_dq[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES],
uint8_t i_isdm_c4_dqs[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES])
{
// Boundary check is done again
uint8_t l_mbapos = 0;
Expand Down Expand Up @@ -1951,8 +1955,27 @@ extern "C" {

if(l_dimmtype != fapi2::ENUM_ATTR_CEN_EFF_CUSTOM_DIMM_YES)
{
FAPI_TRY(isdimmdqs_workaround(i_target_centaur, l_isdm_c4_dqs));
FAPI_TRY(isdimmdq_workaround(i_target_centaur, l_isdm_c4_dq));
if (i_isdm_c4_dq == nullptr)
{
FAPI_TRY(isdimmdq_workaround(i_target_centaur, l_isdm_c4_dq));
}
else
{
std::copy(&i_isdm_c4_dq[0][0],
&i_isdm_c4_dq[0][0] + (MAX_PORTS_PER_CEN * DIMM_TO_C4_DQ_ENTRIES),
&l_isdm_c4_dq[0][0]);
}

if (i_isdm_c4_dqs == nullptr)
{
FAPI_TRY(isdimmdqs_workaround(i_target_centaur, l_isdm_c4_dqs));
}
else
{
std::copy(&i_isdm_c4_dqs[0][0],
&i_isdm_c4_dqs[0][0] + (MAX_PORTS_PER_CEN * DIMM_TO_C4_DQS_ENTRIES),
&l_isdm_c4_dqs[0][0]);
}
}


Expand Down
27 changes: 25 additions & 2 deletions src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -48,6 +48,7 @@
// Includes
//------------------------------------------------------------------------------
#include <fapi2.H>
#include <dimmConsts.H>


//----------------------------------------------------------------------
Expand Down Expand Up @@ -205,6 +206,24 @@ typedef fapi2::ReturnCode (*p9c_mss_access_delay_reg_FP_t)(const fapi2::Target<f

extern "C" {

///
/// @brief Worksaround old VPD that does not have the isdimmdq attribute
/// @param[in] i_target - centaur target on which to operate
/// @param[out] o_isdimm_dq - the attribute data
/// @return fapi2::returnCode
///
fapi2::ReturnCode isdimmdq_workaround(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target,
uint8_t (&o_isdimm_dq)[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES]);

///
/// @brief Worksaround old VPD that does not have the isdimmdq attribute
/// @param[in] i_target - centaur target on which to operate
/// @param[out] o_isdimm_dqs - the attribute data
/// @return fapi2::returnCode
///
fapi2::ReturnCode isdimmdqs_workaround(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target,
uint8_t (&o_isdimm_dqs)[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES]);

/// @brief Reads or Writes delay values
/// @param[in] i_target_mba Reference to centaur.mba target
/// @param[in] i_access_type_e Access type (READ or WRITE)
Expand Down Expand Up @@ -309,13 +328,17 @@ extern "C" {
/// @param[in] i_input_index Input index
/// @param[in] i_verbose 1 = Verbose tracing
/// @param[out] o_value Output C4 bit
/// @param[in] i_isdm_c4_dq optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQ and skip attr access (default = nullptr)
/// @param[in] i_isdm_c4_dqs optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQS and skip attr access (default = nullptr)
/// @return ReturnCode
fapi2::ReturnCode rosetta_map(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba,
const uint8_t i_port,
const input_type i_input_type_e,
uint8_t i_input_index,
const bool i_verbose,
uint8_t& o_value);
uint8_t& o_value,
uint8_t i_isdm_c4_dq[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES] = nullptr,
uint8_t i_isdm_c4_dqs[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES] = nullptr);

/// @brief Gets the rank pair
/// @param[in] i_target_mba Reference to centaur.mba target
Expand Down
40 changes: 28 additions & 12 deletions src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,9 +69,11 @@ extern "C" {
/// @param[in] di DIMM
/// @param[in] r Rank
/// @param[in] p Port
/// @param[in] i_odt_wr nominal write ODT settings
///
PDA_MRS_Storage::PDA_MRS_Storage(const uint8_t ad, const uint32_t an, const uint8_t dr, const uint8_t di,
const uint8_t r, const uint8_t p)
const uint8_t r, const uint8_t p,
const uint8_t (&i_odt_wr)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM])
{
attribute_data = ad;
attribute_name = an;
Expand All @@ -81,6 +83,10 @@ extern "C" {
port = p;
MRS = 0xFF;
pda_string[0] = '\0';

std::copy(&i_odt_wr[0][0][0],
&i_odt_wr[0][0][0] + (MAX_PORTS_PER_MBA * MAX_DIMM_PER_PORT * MAX_RANKS_PER_DIMM),
&odt_wr[0][0][0]);
}

///
Expand Down Expand Up @@ -625,6 +631,9 @@ extern "C" {
dimm = temp.dimm ;
rank = temp.rank ;
port = temp.port ;
std::copy(&odt_wr[0][0][0],
&odt_wr[0][0][0] + (MAX_PORTS_PER_MBA * MAX_DIMM_PER_PORT * MAX_RANKS_PER_DIMM),
&temp.odt_wr[0][0][0]);
}

///
Expand Down Expand Up @@ -668,7 +677,8 @@ extern "C" {
uint32_t l_port_number = 0;
uint32_t dimm_number = i_dimm;
uint32_t rank_number = i_rank;
const uint32_t NUM_POLL = 10;
// Increased polling parameters to avoid CCS hung errors in HB
const uint32_t NUM_POLL = 10000;
const uint32_t WAIT_TIMER = 1500;
uint64_t reg_address = 0;
fapi2::buffer<uint64_t> data_buffer;
Expand Down Expand Up @@ -984,6 +994,7 @@ extern "C" {

//Execute the CCS array
FAPI_INF("Executing the CCS array\n");
FAPI_INF("mss_ddr4_setup_pda: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER);
FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER));
io_ccs_inst_cnt = 0;

Expand Down Expand Up @@ -1047,9 +1058,11 @@ extern "C" {
uint8_t dram_stack[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0};
uint8_t num_spare[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t wr_vref[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t dram_width = 0;
uint8_t array[][2][19] = {{{0x18, 0x18, 0x1c, 0x1c, 0x18, 0x18, 0x1c, 0x1c, 0x18, 0x1c, 0x18, 0x18, 0x1c, 0x1c, 0x1c, 0x18, 0x1c, 0x18, 0x18}, {0x18, 0x1c, 0x20, 0x1c, 0x20, 0x1c, 0x20, 0x20, 0x1c, 0x1c, 0x20, 0x1c, 0x18, 0x1c, 0x1c, 0x1c, 0x1c, 0x18, 0x18}}, {{0x18, 0x1c, 0x1c, 0x1c, 0x20, 0x1c, 0x20, 0x18, 0x18, 0x18, 0x1c, 0x1c, 0x1c, 0x18, 0x18, 0x1c, 0x18, 0x18, 0x1c}, {0x18, 0x1c, 0x18, 0x1c, 0x20, 0x1c, 0x18, 0x1c, 0x20, 0x1c, 0x1c, 0x1c, 0x1c, 0x24, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c}}};
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_STACK_TYPE, i_target, dram_stack));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr));

//get num master ranks per dimm for 3DS
if(dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
Expand Down Expand Up @@ -1119,7 +1132,7 @@ extern "C" {
}

i_pda.push_back(PDA_MRS_Storage(array[port][dimm][dram], fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE, dram, dimm, rank,
port));
port, odt_wr));
FAPI_INF("PDA STRING: %d %s", i_pda.size() - 1, i_pda[i_pda.size() - 1].c_str());
}//for each dram
}//for each rank
Expand Down Expand Up @@ -1199,7 +1212,8 @@ extern "C" {
}

uint32_t io_ccs_inst_cnt = 0;
const uint32_t NUM_POLL = 10;
// Increased polling parameters to avoid CCS hung errors in HB
const uint32_t NUM_POLL = 10000;
const uint32_t WAIT_TIMER = 1500;
fapi2::buffer<uint64_t> data_buffer_64;
fapi2::variable_buffer address_16(16);
Expand Down Expand Up @@ -1236,7 +1250,6 @@ extern "C" {
uint8_t wl_launch_time = 0;
uint8_t odt_hold_time = 0;
uint8_t post_odt_nop_idle = 0;
uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
bool prev_dram_set = false;
vector<PDA_Scom_Storage> scom_storage;
uint8_t prev_dram = 0;
Expand Down Expand Up @@ -1276,7 +1289,6 @@ extern "C" {
FAPI_TRY(rasn_1.clearBit(0, 1));
FAPI_TRY(casn_1.clearBit(0, 1));
FAPI_TRY(wen_1.clearBit(0, 1));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr));

//runs through each PDA command
for(uint32_t i = 0; i < i_pda.size(); i++)
Expand Down Expand Up @@ -1334,7 +1346,7 @@ extern "C" {

FAPI_TRY(mss_disable_cid(i_target, csn_8, cke_4));

FAPI_TRY(odt_4.insert(odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0));
FAPI_TRY(odt_4.insert(i_pda[i].odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0));
// Send out to the CCS array
FAPI_TRY(mss_ccs_inst_arry_0( i_target,
io_ccs_inst_cnt,
Expand Down Expand Up @@ -1417,7 +1429,7 @@ extern "C" {

FAPI_TRY(mss_disable_cid(i_target, csn_8, cke_4));

FAPI_TRY(odt_4.insert(odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0));
FAPI_TRY(odt_4.insert(i_pda[i].odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0));

// Send out to the CCS array
FAPI_TRY(mss_ccs_inst_arry_0( i_target,
Expand Down Expand Up @@ -1513,6 +1525,7 @@ extern "C" {

//Execute the CCS array
FAPI_INF("Executing the CCS array\n");
FAPI_INF("mss_ddr4_run_pda_by_dimm_rank: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER);
FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER));
io_ccs_inst_cnt = 0;

Expand Down Expand Up @@ -1590,7 +1603,7 @@ extern "C" {
FAPI_TRY(address_16_backup.insert(address_16, 0, 16, 0));
FAPI_TRY(bank_3_backup.clearBit(0, 3));
FAPI_TRY(bank_3_backup.insert(bank_3, 0, 3, 0));
FAPI_TRY(odt_4.insert(odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0));
FAPI_TRY(odt_4.insert(i_pda[0].odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0));

//loads the previous DRAM
if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0))
Expand Down Expand Up @@ -1778,6 +1791,7 @@ extern "C" {

//Execute the CCS array
FAPI_INF("Executing the CCS array\n");
FAPI_INF("mss_ddr4_run_pda_by_dimm_rank: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER);
FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER));

//loops through and clears out the storage class
Expand Down Expand Up @@ -1873,7 +1887,8 @@ extern "C" {
uint32_t l_port_number = 0;
uint32_t dimm_number = i_dimm;
uint32_t rank_number = i_rank;
const uint32_t NUM_POLL = 10;
// Increased polling parameters to avoid CCS hung errors in HB
const uint32_t NUM_POLL = 10000;
const uint32_t WAIT_TIMER = 1500;
uint64_t reg_address = 0;
fapi2::buffer<uint64_t> data_buffer;
Expand Down Expand Up @@ -1905,11 +1920,11 @@ extern "C" {
fapi2::variable_buffer csn_8_odt(8);
uint8_t dram_gen = 0;
fapi2::variable_buffer mrs3(16);
uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t dram_stack[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0};
uint8_t dimm_type = 0;
uint8_t is_sim = 0;
uint8_t address_mirror_map[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0}; //address_mirror_map[port][dimm]
uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t mpr_op = 0; // MPR Op
uint8_t mpr_page = 0; // MPR Page Selection
uint8_t geardown_mode = 0; // Gear Down Mode
Expand All @@ -1933,11 +1948,11 @@ extern "C" {
FAPI_TRY(csn_8_odt.clearBit(7, 1));

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_GEN, i_target, dram_gen));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_STACK_TYPE, i_target, dram_stack));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DIMM_TYPE, i_target, dimm_type));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), is_sim));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_ADDRESS_MIRRORING, i_target, address_mirror_map));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr));

// WORKAROUNDS
FAPI_TRY(fapi2::getScom(i_target, CEN_MBA_CCS_MODEQ, data_buffer));
Expand Down Expand Up @@ -2209,6 +2224,7 @@ extern "C" {

//Execute the CCS array
FAPI_INF("Executing the CCS array\n");
FAPI_INF("mss_ddr4_disable_pda: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER);
FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER));

//Disable CCS
Expand Down
5 changes: 4 additions & 1 deletion src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@
#define _MSS_DDR4_PDA_H
#include <fapi2.H>
#include <vector>
#include <dimmConsts.H>
using namespace std;

extern "C"
Expand All @@ -57,6 +58,7 @@ extern "C"
uint8_t dram;
uint8_t rank;
uint8_t port;
uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM];

///
/// @brief PDA MRS storage constructor
Expand All @@ -66,9 +68,10 @@ extern "C"
/// @param[in] di DIMM position
/// @param[in] r rank
/// @param[in] p port
/// @param[in] i_odt_wr nominal write ODT settings
///
PDA_MRS_Storage(const uint8_t ad, const uint32_t an, const uint8_t dr, const uint8_t di, const uint8_t r,
const uint8_t p);
const uint8_t p, const uint8_t (&i_odt_wr)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM]);

///
/// @brief Destructor
Expand Down

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