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Added port of MRS engine to generic
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Change-Id: If2715325eb4a924a265d772f2a8339358ffadd99
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86882
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89475
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
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Matthickman14 authored and crgeddes committed Mar 26, 2020
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1 change: 1 addition & 0 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C
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Expand Up @@ -34,6 +34,7 @@
// *HWP Consumed by: FSP:HB

#include <lib/shared/exp_consts.H>
#include <lib/shared/exp_defaults.H>
#include <lib/inband/exp_inband.H>
#include <generic/memory/lib/utils/c_str.H>
#include <generic/memory/lib/utils/mss_bad_bits.H>
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28 changes: 28 additions & 0 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H
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Expand Up @@ -194,6 +194,34 @@ class ccsTraits<mss::mc_type::EXPLORER>
STAT_HUNG = 0x0ull,
};

// Map bits in the ARR0 register(s) to MRS address bits. Should be traits related to ARR0. BRS
enum address_bits
{
A0 = 0,
A1 = 1,
A2 = 2,
A3 = 3,
A4 = 4,
A5 = 5,
A6 = 6,
A7 = 7,
A8 = 8,
A9 = 9,
A10 = 10,
A11 = 11,
A12 = 12,
A13 = 13,
A14 = ARR0_DDR_ADDRESS_14,
A15 = ARR0_DDR_ADDRESS_15,
A16 = ARR0_DDR_ADDRESS_16,
A17 = ARR0_DDR_ADDRESS_17,

// Only kind of address bits ... <shrug>
BA0 = 17,
BA1 = 18,
BG0 = 19,
BG1 = 15,
};

// CSN Regular Settings
static constexpr std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] =
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211 changes: 210 additions & 1 deletion src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_mrs_traits.H
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2020 */
/* Contributors Listed Below - COPYRIGHT 2019,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand All @@ -22,3 +22,212 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */

///
/// @file exp_mrs_traits.H
/// @brief Contains the mc specific traits and settings for the mrs engine
///
// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: HB:FSP

#ifndef _EXP_MRS_TRAITS_H_
#define _EXP_MRS_TRAITS_H_

#include <fapi2.H>
#include <explorer_scom_addresses.H>
#include <explorer_scom_addresses_fld.H>
#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
#include <lib/shared/exp_defaults.H>

#include <generic/memory/lib/utils/mss_rank.H>
#include <generic/memory/lib/utils/find.H>
#include <lib/shared/exp_consts.H>
#include <lib/exp_attribute_accessors_manual.H>
#include <lib/mc/exp_port.H>
#include <generic/memory/lib/dimm/mrs_traits.H>

///
/// @class mrsTraits
/// @brief Nimbus MRS Engine traits
///
template<>
class mrsTraits<mss::mc_type::EXPLORER>
{
public:

static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT;
static constexpr uint64_t TCCD_S = 4;
static constexpr uint64_t TMRD = 16;

///
/// @brief Returns an error for bad mrs parameter
/// @return mrs error
///
static fapi2::MSS_BAD_MR_PARAMETER bad_mr_parameter()
{
return fapi2::MSS_BAD_MR_PARAMETER();
}

///
/// @brief Returns if rcd mirror mode on
/// @return false, currently set to disabled
///
static uint8_t attr_mirror_mode_on()
{
constexpr uint8_t MIRRORED = 0x01;
return MIRRORED;
}

///
/// @brief Returns if mirror mode is enabled, currently set to disabled
/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
/// @param[out] ref to the value uint8_t
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
///
static fapi2::ReturnCode mirror_mode(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
uint8_t& o_value)
{
return mss::attr::get_exp_dram_address_mirroring(i_target, o_value);
}

///
/// @brief Calls the get_dimm_target_from_rank port api
/// @param[in] i_target the port target
/// @param[in] i_port_rank the port rank number
/// @param[out] o_dimm the DIMM target
/// @return FAPI2_RC_SUCCESS iff all is ok, FAPI2_RC_INVALID_PARAMETER otherwise
///
static fapi2::ReturnCode get_dimm_target_wrap (const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
const uint64_t i_port_rank,
fapi2::Target<fapi2::TARGET_TYPE_DIMM>& o_dimm)
{
fapi2::ReturnCode l_rc;
auto l_rank_info = mss::rank::info<mss::mc_type::EXPLORER>(i_target, i_port_rank, l_rc);
FAPI_TRY (l_rc);
o_dimm = l_rank_info.get_dimm_target();

fapi_try_exit:
return l_rc;
}

///
/// @brief Calls the ATTR_EFF_DRAM_TCCD_L getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t& reference to store the value
/// @return FAPI2_RC_SUCCESS iff all is ok, FAPI2_RC_INVALID_PARAMETER otherwise
///
static fapi2::ReturnCode dram_tccd_l (const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value)
{
return mss::attr::get_dram_tccd_l(i_target, o_value);
}

///
/// @brief Calls the ATTR_EFF_DRAM_TRP getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t& reference to store the value
/// @return FAPI2_RC_SUCCESS iff all is ok, FAPI2_RC_INVALID_PARAMETER otherwise
///
static fapi2::ReturnCode dram_trp (const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value)
{
return mss::attr::get_dram_trp(i_target, o_value);
}

///
/// @brief Calls the ATTR_EFF_DRAM_TCCD_L getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t& reference to store the value
/// @return FAPI2_RC_SUCCESS iff all is ok, FAPI2_RC_INVALID_PARAMETER otherwise
///
static fapi2::ReturnCode dram_tccd_l (const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
auto l_port_target = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
return mss::attr::get_dram_tccd_l(l_port_target, o_value);
}

///
/// @brief Calls the ATTR_EFF_DRAM_TRP getter
/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
/// @param[out] uint8_t& reference to store the value
/// @return FAPI2_RC_SUCCESS iff all is ok, FAPI2_RC_INVALID_PARAMETER otherwise
///
static fapi2::ReturnCode dram_trp (const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
{
auto l_port_target = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target);
return mss::attr::get_dram_trp(l_port_target, o_value);
}

///
/// @brief Calls the tmod timing api
/// @tparam T fapi2::TargetType of the target used to calculate cycles from ns
/// @param[in] i_target the target used to get clocks
/// @return max(24nCK,15ns) in clocks
/// @note Returning the worst case tMOD - 24 nCK
///
template < fapi2::TargetType T >
static uint64_t mrs_tmod( const fapi2::Target<T>& i_target )
{
constexpr uint64_t WORST_CASE_TMOD = 24;
return WORST_CASE_TMOD;
}

// Enum for the nibble locations in register
enum nibble : size_t
{
LOWER = 2,
UPPER = 3,
};

// function space and control word definitions
// Need verification
enum db02_def : size_t
{
// Function spaces
FUNC_SPACE_0 = 0,
FUNC_SPACE_1 = 1,
FUNC_SPACE_2 = 2,
FUNC_SPACE_3 = 3,
FUNC_SPACE_4 = 4,
FUNC_SPACE_5 = 5,
FUNC_SPACE_6 = 6,
FUNC_SPACE_7 = 7,

// From DB02 spec - F[3:0]BC7x control word
MAX_FUNC_SPACE = FUNC_SPACE_7,

// 4 bit BCWs
DQ_RTT_NOM_CW = 0x0,
DQ_RTT_WR_CW = 0x1,
DQ_RTT_PARK_CW = 0x2,
DQ_DRIVER_CW = 0x3,
MDQ_RTT_CW = 0x4,
MDQ_DRIVER_CW = 0x5,
CMD_SPACE_CW = 0x6,
RANK_PRESENCE_CW = 0x7,
RANK_SELECTION_CW = 0x8,
POWER_SAVING_CW = 0x9,
OPERATING_SPEED = 0xA,
VOLT_AND_SLEW_RATE_CW = 0xB,
BUFF_TRAIN_MODE_CW = 0xC,
LDQ_OPERATION_CW = 0xD,
PARITY_CW = 0xE,
ERROR_STATUS_CW = 0xF,
FUNC_SPACE_SELECT_CW = 0x7,

// 8 bit BCWs
BUFF_CONFIG_CW = 0x1, // Func space 0
LRDIMM_OPERATING_SPEED = 0x6, // Func space 0
HOST_DFE = 0xE, // Func space 2
HOST_VREF_CW = 0x5, // Func space 5
DRAM_VREF_CW = 0x6, // Func space 5
BUFF_TRAIN_CONFIG_CW = 0x4, // Func space 6

// Safe delays for BCW's
BCW_SAFE_DELAY = 2000,
};

};

#endif
1 change: 1 addition & 0 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C
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Expand Up @@ -33,6 +33,7 @@
// *HWP Consumed by: FSP:HB

#include <generic/memory/lib/utils/c_str.H>
#include <lib/shared/exp_defaults.H>
#include <lib/exp_draminit_utils.H>
#include <lib/phy/exp_train_display.H>
#include <lib/phy/exp_train_handler.H>
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3 changes: 1 addition & 2 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* Contributors Listed Below - COPYRIGHT 2018,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -37,7 +37,6 @@
#define __MSS_EXP_DRAMINIT_UTILS__

#include <fapi2.H>
#include <lib/shared/exp_defaults.H>
#include <lib/dimm/exp_rank.H>
#include <lib/shared/exp_consts.H>
#include <exp_data_structs.H>
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3 changes: 2 additions & 1 deletion src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2019 */
/* Contributors Listed Below - COPYRIGHT 2019,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -34,6 +34,7 @@
// *HWP Consumed by: FSP:HB

#include <fapi2.H>
#include <lib/shared/exp_defaults.H>
#include <lib/shared/exp_consts.H>
#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
#include <generic/memory/lib/utils/index.H>
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1 change: 0 additions & 1 deletion src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.H
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Expand Up @@ -38,7 +38,6 @@

#include <fapi2.H>
#include <lib/shared/exp_consts.H>
#include <lib/shared/exp_defaults.H>
#include <lib/dimm/exp_rank.H>
#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
#include <generic/memory/lib/utils/index.H>
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1 change: 1 addition & 0 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C
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Expand Up @@ -34,6 +34,7 @@
// *HWP Consumed by: FSP:HB

#include <fapi2.H>
#include <lib/shared/exp_defaults.H>
#include <lib/shared/exp_consts.H>
#include <exp_data_structs.H>
#include <generic/memory/lib/utils/mss_bad_bits.H>
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3 changes: 1 addition & 2 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2019 */
/* Contributors Listed Below - COPYRIGHT 2019,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -38,7 +38,6 @@

#include <fapi2.H>
#include <lib/shared/exp_consts.H>
#include <lib/shared/exp_defaults.H>
#include <lib/dimm/exp_rank.H>
#include <exp_data_structs.H>
#include <generic/memory/lib/utils/endian_utils.H>
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3 changes: 2 additions & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C
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Expand Up @@ -35,10 +35,11 @@

#include <fapi2.H>

#include <lib/shared/nimbus_defaults.H>
#include <lib/dimm/mrs_traits_nimbus.H>
#include <mss.H>
#include <lib/fir/check.H>
#include <lib/phy/mss_lrdimm_training.H>
#include <lib/shared/nimbus_defaults.H>
#include <lib/ccs/ccs_traits_nimbus.H>
#include <generic/memory/lib/ccs/ccs.H>
#include <lib/ccs/ccs_nimbus.H>
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29 changes: 29 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H
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Expand Up @@ -67,6 +67,7 @@ class ccsTraits<mss::mc_type::NIMBUS>
static constexpr uint64_t NTTM_READ_DELAY = 0x40;
static constexpr uint64_t NTTM_MODE_FORCE_READ = 33;

static constexpr uint64_t DDR_ADDRESS_12 = 12;

// Command Pass Disable Delay Time for Nimbus
static constexpr uint64_t TIMING_TCPDED = 4;
Expand Down Expand Up @@ -207,6 +208,34 @@ class ccsTraits<mss::mc_type::NIMBUS>
STAT_HUNG = 0x0ull,
};

// Map bits in the ARR0 register(s) to MRS address bits. Should be traits related to ARR0. BRS
enum address_bits
{
A0 = 0,
A1 = 1,
A2 = 2,
A3 = 3,
A4 = 4,
A5 = 5,
A6 = 6,
A7 = 7,
A8 = 8,
A9 = 9,
A10 = 10,
A11 = 11,
A12 = 12,
A13 = 13,
A14 = ARR0_DDR_ADDRESS_14,
A15 = ARR0_DDR_ADDRESS_15,
A16 = ARR0_DDR_ADDRESS_16,
A17 = ARR0_DDR_ADDRESS_17,

// Only kind of address bits ... <shrug>
BA0 = 17,
BA1 = 18,
BG0 = 19,
BG1 = 15,
};

// CSN Regular Settings
static constexpr std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] =
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