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Added security bit and fir handling, gard and trace fixes
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Change-Id: I8160d9662859232dfd612b3a2f5c1c522c02e308
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82534
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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@Matthickman14 @dcrowell77
Matthickman14 authored and dcrowell77 committed Aug 28, 2019
1 parent 845fb44 commit 01ac1b8
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Showing 7 changed files with 273 additions and 113 deletions.
3 changes: 3 additions & 0 deletions src/usr/isteps/nvdimm/errlud_nvdimm.C
View file
Expand Up @@ -178,6 +178,8 @@ UdNvdimmOPParms::UdNvdimmOPParms( const nvdimm_reg_t &i_RegInfo )
// 1 byte : CSAVE_INFO
// 1 byte : CSAVE_FAIL_INFO0
// 1 byte : CSAVE_FAIL_INFO1
// 1 byte : CSAVE_TIMEOUT_INFO0
// 1 byte : CSAVE_TIMEOUT_INFO1
// 1 byte : ERROR_THRESHOLD_STATUS
// 1 byte : NVDIMM_READY
// 1 byte : NVDIMM_CMD_STATUS0
Expand All @@ -192,6 +194,7 @@ UdNvdimmOPParms::UdNvdimmOPParms( const nvdimm_reg_t &i_RegInfo )
// 1 byte : RESTORE_TIMEOUT1
// 1 byte : ARM_STATUS
// 1 byte : SET_EVENT_NOTIFICATION_STATUS
// 1 byte : ENCRYPTION_CONFIG_STATUS

char * l_pBuf = reinterpret_cast<char *>( reallocUsrBuf(sizeof(i_RegInfo)));
memcpy(l_pBuf, &i_RegInfo, sizeof(i_RegInfo));
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59 changes: 32 additions & 27 deletions src/usr/isteps/nvdimm/nvdimm.C
View file
Expand Up @@ -131,6 +131,10 @@ static constexpr size_t MAX_TPM_SIZE = 34;
static constexpr uint8_t KEY_TERMINATE_BYTE = 0x00;
static constexpr uint8_t KEY_ABORT_BYTE = 0xFF;

// NVDIMM CSAVE_FAIL_INFO1 Bit mask
// Currently only bits 1:6 need to be checked during init
static constexpr uint8_t CSAVE_FAIL_BITS_MASK = 0x7E;

#ifndef __HOSTBOOT_RUNTIME
// Warning thresholds
static constexpr uint8_t THRESHOLD_ES_LIFETIME = 0x07; // 7%
Expand Down Expand Up @@ -552,8 +556,7 @@ errlHndl_t nvdimmReady(Target *i_nvdimm)

// If nvdimm is not ready for access by now, this is
// a failing indication on the NV controller
l_err->addPartCallout( i_nvdimm,
HWAS::NV_CONTROLLER_PART_TYPE,
l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
Expand Down Expand Up @@ -1245,17 +1248,8 @@ errlHndl_t nvdimmRestore(TargetHandleList& i_nvdimmList, uint8_t &i_mpipl)
ERRORLOG::ErrlEntry::NO_SW_CALLOUT);
break;
}
}

if (l_err)
{
TRACFCOMP(g_trac_nvdimm, "restore encountered an error");
break;
}

// Exit self-refresh
for (const auto & l_nvdimm : i_nvdimmList)
{
// Exit self-refresh
TargetHandleList l_mcaList;
getParentAffinityTargets(l_mcaList, l_nvdimm, CLASS_UNIT, TYPE_MCA);
assert(l_mcaList.size(), "nvdimmRestore() failed to find parent MCA.");
Expand Down Expand Up @@ -1344,12 +1338,10 @@ errlHndl_t nvdimmEraseCheck(Target *i_nvdimm)
{
// For both Erase timeout and Erase fail
// Callout nvdimm on high, gard and deconfig
l_err->addPartCallout( i_nvdimm,
HWAS::NV_CONTROLLER_PART_TYPE,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);

l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);

// Collect register data for FFDC Traces
nvdimmTraceRegs ( i_nvdimm, l_RegInfo );
Expand Down Expand Up @@ -1721,8 +1713,7 @@ errlHndl_t nvdimm_restore(TargetHandleList &i_nvdimmList)

// Invalid restore could be due to dram not in self-refresh
// or controller issue. Data should not be trusted at this point
l_err->addPartCallout( l_nvdimm,
HWAS::NV_CONTROLLER_PART_TYPE,
l_err->addHwCallout( l_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
Expand Down Expand Up @@ -1901,6 +1892,8 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
errlHndl_t l_err = nullptr;
bool l_continue = true;
uint8_t l_data = 0;
uint8_t l_failinfo0 = 0;
uint8_t l_failinfo1 = 0;
nvdimm_reg_t l_RegInfo;
uint32_t l_poll = 0;

Expand Down Expand Up @@ -2015,8 +2008,7 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
{
// May have to move the error handling to the caller
// as different op could have different error severity
l_err->addPartCallout( i_nvdimm,
HWAS::NV_CONTROLLER_PART_TYPE,
l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
Expand All @@ -2027,13 +2019,27 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
}
}

// Check CSAVE_ERROR Register
l_err = nvdimmReadReg( i_nvdimm, CSAVE_FAIL_INFO0, l_data );
// Check CSAVE FAIL INFO registers for fail errors
l_err = nvdimmReadReg( i_nvdimm, CSAVE_FAIL_INFO0, l_failinfo0 );
if (l_err)
{
break;
}
else if (l_data != ZERO)
l_err = nvdimmReadReg ( i_nvdimm, CSAVE_FAIL_INFO1, l_failinfo1 );
if (l_err)
{
break;
}
// Apply mask for relevant 1:6 bits to failinfo1
l_failinfo1 &= CSAVE_FAIL_BITS_MASK;

// Check CSAVE_STATUS Register
l_err = nvdimmReadReg( i_nvdimm, CSAVE_STATUS, l_data );
if (l_err)
{
break;
}
else if ((l_data == SAVE_ERROR) && ((l_failinfo0 != ZERO) || (l_failinfo1 != ZERO)))
{
/*@
*@errortype
Expand Down Expand Up @@ -2066,8 +2072,7 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
if ( l_RegInfo.CSave_Info != VALID_IMAGE )
{
// Callout and gard dimm if image is not valid
l_err->addPartCallout( i_nvdimm,
HWAS::NV_CONTROLLER_PART_TYPE,
l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
Expand Down
23 changes: 23 additions & 0 deletions src/usr/isteps/nvdimm/nvdimm.H
View file
Expand Up @@ -354,6 +354,8 @@ enum i2c_out_values : uint8_t
ES_POLICY_ERROR = 0x02,
ARM_ERROR = 0X02,
RSTR_ERROR = 0x02,
SAVE_ERROR = 0x02,
ARM_CLEAR = 0x20,
};

// Timeout-related enum
Expand Down Expand Up @@ -467,7 +469,28 @@ enum event_n : uint8_t
{
PERSISTENCY_NOTIFICATION = 0x01,
SET_EVENT_NOTIFICATION_ERROR = 0x02,
WARNING_THRESHOLD_NOTIFICATION = 0x02,
PERSISTENCY_ENABLED = 0x04,
WARNING_THRESHOLD_ENABLED = 0x08,
ENABLE_NOTIFICATIONS = 0x03,
NOTIFICATIONS_ENABLED = 0x0C,
};

// MBACALFIR register addresses
enum mbacal_addresses : uint32_t
{
MBACALFIR_AND_MASK_REG = 0x07010904,
MBACALFIR_OR_MASK_REG = 0x07010905,
MBACALFIR_ACTION0_REG = 0x07010906,
MBACALFIR_ACTION1_REG = 0x07010907,
};

// MBACALFIR bit masks for event n
enum mbacal_bitmask_values : uint64_t
{
MBACALFIR_EVENTN_AND_BIT = 0xff7fffffffffffff,
MBACALFIR_EVENTN_OR_BIT = 0x0080000000000000,
MBACALFIR_UNMASK_BIT = 0xff7fffffffffffff,
};

/**
Expand Down

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