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HW403465 applies to all chips; Revert NDD2.1 RL; add SW406970
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Per Ron Kalla's request, NDD2.1 should not use risklevel

Change-Id: I0bfbd1619e0b64061234680eac642aef4937d212
Original-Change-Id: I2354c2523d760ac16f7c4c2429003ef07e58225d
CQ: HW403465
CQ: SW406970
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49148
Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55589
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@jklazyns @dcrowell77
jklazyns authored and dcrowell77 committed Mar 13, 2018
1 parent 3d3f11d commit 0e5d5b7
Showing 1 changed file with 28 additions and 23 deletions.
51 changes: 28 additions & 23 deletions src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -723,6 +723,30 @@
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_SW406970</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
SW406970 - SCOM clockgating issue
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x22</value>
<test>LESS_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x10</value>
<test>EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_HW362088</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
Expand Down Expand Up @@ -2642,25 +2666,6 @@
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_HW403465</id>>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
Nimbus DD1.0 DD2.0
L1 access latency increases when data footprint should still
be within L1 cache size. Revert L1 LRU changes
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x20</value>
<test>LESS_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_HW402145</id>>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
Expand Down Expand Up @@ -3885,21 +3890,21 @@
<id>ATTR_CHIP_EC_FEATURE_HW417829</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
HW417829 - Bad rfscv branch
HW417829 / HW423787 - Bad rfscv branch
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x20</value>
<test>GREATER_THAN_OR_EQUAL</test>
<value>0x21</value>
<test>LESS_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
<test>EQUAL</test>
</ec>
</chip>
</chipEcFeature>
Expand Down

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