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Updating Channel Fail Mask
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- Changing the phy channel fail mask so that
    a to many bus errors will only trigger a channel fail

Change-Id: I53a161687da432a0dd41f9dfdb3667581b79b2cf
CQ: SW433478
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60815
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Gary A. Peterson <garyp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60826
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@steffenchris @dcrowell77
steffenchris authored and dcrowell77 committed Jun 25, 2018
1 parent 49fe793 commit 13b4227
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Showing 3 changed files with 17 additions and 5 deletions.
11 changes: 11 additions & 0 deletions src/import/chips/p9/procedures/hwp/io/p9_io_dmi_scominit.C
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,7 @@ const uint64_t FIR_ACTION0 = 0x0000000000000000ULL;
const uint64_t FIR_ACTION1 = 0x2068686868000000ULL;
const uint64_t FIR_MASK = 0xDF97979797FFC000ULL;


const uint64_t DMI_FIR_ACTION0_REG = 0x07011006;
const uint64_t DMI_FIR_ACTION1_REG = 0x07011007;
const uint64_t DMI_FIR_MASK_REG = 0x07011003;
Expand Down Expand Up @@ -104,6 +105,7 @@ fapi2::ReturnCode p9_io_dmi_scominit(const DMI_TGT& i_tgt)
// mark HWP entry
FAPI_INF("p9_io_dmi_scominit: Entering ...");
const uint8_t GRP_03 = 3;
const uint8_t GRP_00 = 0;
const uint8_t LANE_00 = 0;
fapi2::ReturnCode rc = fapi2::FAPI2_RC_SUCCESS;

Expand Down Expand Up @@ -136,6 +138,15 @@ fapi2::ReturnCode p9_io_dmi_scominit(const DMI_TGT& i_tgt)
fapi2::current_err = rc;
}

// Configure Channel Fail Mask
{
fapi2::Target<fapi2::TARGET_TYPE_MC> l_mc_tgt =
i_tgt.getParent<fapi2::TARGET_TYPE_MC>();

// Set the Channel Fail Mask so only too many bus errors triggers a channel fail.
FAPI_TRY(io::rmw(EDIP_CHAN_FAIL_MASK, l_mc_tgt, GRP_00, LANE_00, 0x08));
}

// configure FIR
{
fapi2::Target<fapi2::TARGET_TYPE_MC> l_mc_tgt =
Expand Down
3 changes: 2 additions & 1 deletion src/import/chips/p9/procedures/hwp/io/p9_io_regs.H
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -192,6 +192,7 @@
#define EDIP_RX_USERDEF_TIMEOUT 0x800888000000003f, 52, 4 // rx_userdef_timeout timeout used when using the user defined servo ops (see workbook table 4.10 for timer settings)
#define EDIP_RX_BER_TIMEOUT 0x800888000000003f, 56, 4 // rx_ber_timeout, used for when making bit error measurements with a servo op (see workbook table 4.10 for timer settings)
#define EDIP_RX_CTL_MODE16_EO_PG 0x800888000000003f, 48, 16 // register -- description
#define EDIP_CHAN_FAIL_MASK 0x0000000000000020, 15, 8 // scom mode reg spares.


#define EDI_RX_WTM_STATE 0x800950000000003f, 48, 5 // main wiretest state machine current state (rjr)): \r\n\tx00: idle \r\n\tx01: drv data wt \r\n\tx02: drv clock wt \r\n\tx03: drv data 0 \r\n\tx04: drv clock 0 \r\n\tx05: rx wt \r\n\tx06: wait all ones \r\n\tx07: reset pll \r\n\tx08: wait pll \r\n\tx09: drive clock \r\n\tx0a: drive data 1 \r\n\tx0b: wait all zeroes \r\n\tx0c: drive data 0 \r\n\tx0d: done \r\n\tx0e: unused \r\n\tx0f: unused \r\n\tx10: wait prev done \r\n\tx11: drv prev done \r\n\tx12: drv all done \r\n\tx13: wait all done \r\n\tx14: init tx fifo \r\n\tx15: unused \r\n\tx16: unused \r\n\tx17: unused \r\n\tx18: set c & d dr strength \r\n\tx19: set data only dr strength \r\n\tx1a: clock fail \r\n\tx1b: all bad lanes \r\n\tx1c: wt timeout fail \r\n\tx1d: pll/dll fail \r\n\tx1e: all ones fail \r\n\tx1f: all zeroes fail \r\n\trjr
Expand Down
8 changes: 4 additions & 4 deletions src/import/chips/p9/procedures/hwp/io/p9_io_scom.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -56,7 +56,7 @@
#define P9_OBUS1_PHY_BASE_0x0A010C00 0x0A010C00
#define P9_OBUS2_PHY_BASE_0x0B010C00 0x0B010C00
#define P9_OBUS3_PHY_BASE_0x0C010C00 0x0C010C00
#define P9_DMI0_PHY_BASE_0x0701103F 0x0701103F
#define P9_DMI0_PHY_BASE_0x07011000 0x07011000
#define CEN_PHY_BASE_0x02010400 0x02010400

//-----------------------------------------------------------------------------
Expand Down Expand Up @@ -132,11 +132,11 @@ inline uint32_t get_base_address( const fapi2::Target < K > i_target, uint32_t&
break;

case fapi2::TargetType::TARGET_TYPE_DMI:
o_base_addr = P9_DMI0_PHY_BASE_0x0701103F;
o_base_addr = P9_DMI0_PHY_BASE_0x07011000;
break;

case fapi2::TargetType::TARGET_TYPE_MC:
o_base_addr = P9_DMI0_PHY_BASE_0x0701103F;
o_base_addr = P9_DMI0_PHY_BASE_0x07011000;
break;

case fapi2::TargetType::TARGET_TYPE_ABUS:
Expand Down

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