pmic_enable: Add additional clear for error status bits in R04-R07

2U IDTs have an issue that will continue to be investigated
regarding an SWD_UNDER_VOLTAGE_LOCKOUT error that propogates
up to flag some additional error bits. These bits apparently
aren't cleared by the current method of the 1-shot write to
register R14, but this additional clear will do so. This at
least will clear the errors so they don't linger for
subsequent runs, though the cause of the issue still is being
investigated.

Change-Id: I48ba256dfbf1149a1286fef5379943a80613855e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/93330
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/93333
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>

src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C

@@ -359,6 +359,7 @@ fapi2::ReturnCode clear(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_tar
 {
     using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>;
     using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>;
+    using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>;
 
     fapi2::buffer<uint8_t> l_reg_contents;
     FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R14, l_reg_contents));
@@ -367,6 +368,10 @@ fapi2::ReturnCode clear(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_tar
     l_reg_contents.setBit<FIELDS::R14_GLOBAL_CLEAR_STATUS>();
     FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R14, l_reg_contents));
 
+    // Clear host region codes
+    l_reg_contents = CONSTS::CLEAR_R04_TO_R07;
+    FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R39_COMMAND_CODES, l_reg_contents));
+
 fapi_try_exit:
     return fapi2::current_err;
 }

src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H

@@ -257,8 +257,11 @@ struct consts<mss::pmic::product::JEDEC_COMPLIANT>
 
     static constexpr uint8_t VENDOR_PASSWORD_LOW        = 0x73;
     static constexpr uint8_t VENDOR_PASSWORD_HIGH       = 0x94;
+
+    // Codes below for R39
     static constexpr uint8_t UNLOCK_VENDOR_REGION       = 0x40;
     static constexpr uint8_t LOCK_VENDOR_REGION         = 0x00;
+    static constexpr uint8_t CLEAR_R04_TO_R07           = 0x74;
     static constexpr uint8_t BURN_R40_TO_R4F            = 0x81;
     static constexpr uint8_t BURN_R50_TO_R5F            = 0x82;
     static constexpr uint8_t BURN_R60_TO_R6F            = 0x85; // TI spec says 0x83, is that a deviation or a typo?