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Enable mixed core xlate; Enable xlate protection feature; Disable LSU…
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… clockgate

Change-Id: I1fbc2c79330520d6033adfafe85a89fc71ed3fb0
CQ: HW437820
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53911
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53918
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@jklazyns @dcrowell77
jklazyns authored and dcrowell77 committed Feb 18, 2018
1 parent f28cb33 commit 1c8193d
Showing 1 changed file with 72 additions and 0 deletions.
72 changes: 72 additions & 0 deletions src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
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Expand Up @@ -3316,6 +3316,78 @@
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_PREVENT_Q0_HV_ACCESS</id>>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
Enable feature, preventing access to quadrant 0 in hypervisor mode when LPIDR != 0
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x22</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x11</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_MIXED_CORE_XLATE</id>>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
Enable mixed core (HPT/Radix) translation
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x22</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x11</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_HW437820</id>>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
HW437820 - LSU clockgating issue
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x22</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x11</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_HW407165</id>>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
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