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Clear INT_PC registers on MPIPL when initializing intrrp
During MPIPL the SBE issues a sync_reset command to the XIVE logic. There is an issue in the HW logic that is leaving some of the INT_PC registers filled in. We need to make sure those are cleared before reinitializing the interrupt resource provide for MPIPL Change-Id: I7a8134d067e3758095e910d739702636da0e8a79 RTC: 172905 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46836 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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