PM: Add atrribute to cpmmr control for Core Periodic Quiesce

Change-Id: I70cc9bba5e358a85ee420b329365817c688084f0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45505
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45510
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H

@@ -228,7 +228,6 @@ HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS,              0x10000000)
 HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS,    0x08000000)
 HCD_CONST(SGPE_VDM_ENABLE_BIT_POS,                0x04000000)
 HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS,     0x02000000)
-HCD_CONST(SGPE_CORE_PERIODIC_QUIESCE_DISABLE_POS, 0x01000000)
 HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS,        0x00004000)
 HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS,     0x00002000)
 HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS,       0x00001000)

src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h

@@ -241,6 +241,16 @@ enum PM_PGPE_HEADER_FLAGS
     PGPE_HEADER_FLAGS_VRATIO_MODIFIER               = 12
 };
 
+//
+//Enum for of PPM Register Bits for FW Usage
+//
+enum PM_PPM_FW_FLAGS
+{
+    CPPM_CPMMR_DISABLE_PERIODIC_CORE_QUIESCE        = 2,
+    QPPM_QCCR_IGNORE_QUAD_STOP_EXITS                = 10,
+    QPPM_QCCR_IGNORE_QUAD_STOP_ENTRIES              = 11
+};
+
 #ifndef __PPE_PLAT
 } //End p9hcd namespace
 #endif

src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C

@@ -936,18 +936,6 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO
 
     FAPI_DBG("Cache DC Adjust Disabled      :   %s", attrVal ? "TRUE" : "FALSE" );
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE,
-                           FAPI_SYSTEM,
-                           attrVal),
-             "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE");
-
-    if( attrVal )
-    {
-        sgpeFlag |= SGPE_CORE_PERIODIC_QUIESCE_DISABLE_POS;
-    }
-
-    FAPI_DBG("Core Periodic Quiesce Disabled:   %s", attrVal ? "TRUE" : "FALSE" );
-
     // Set PGPE Header Flags from Attributes
     FAPI_DBG(" -------------------- PGPE Flags -----------------");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE,

src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C

@@ -130,7 +130,10 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
     const char* PM_MODE_NAME_VAR; //Defines storage for PM_MODE_NAME
     FAPI_INF("Executing p9_stop_gpe_init in mode %s", PM_MODE_NAME(i_mode));
 
-    uint8_t  fusedModeState = 0;
+    uint8_t                 fusedModeState = 0;
+    uint8_t                 coreQuiesceDis = 0;
+    uint8_t                 l_core_number  = 0;
+    fapi2::buffer<uint64_t> l_data64       = 0;
 
     // -------------------------------
     // Initialization:  perform order or dynamic operations to initialize
@@ -143,6 +146,11 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
                                fusedModeState),
                  "Error from FAPI_ATTR_GET for attribute ATTR_FUSED_CORE_MODE");
 
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE,
+                               FAPI_SYSTEM,
+                               coreQuiesceDis),
+                 "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE");
+
         // Check each core has a functional EX and EQ
         auto l_functional_core_vector =
             i_target.getChildren<fapi2::TARGET_TYPE_CORE>
@@ -189,9 +197,6 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
         //Additional settings for fused mode
         if (fusedModeState == 1)
         {
-            uint8_t                 l_core_number = 0;
-            fapi2::buffer<uint64_t> l_data64      = 0;
-
             auto l_functional_core_vector =
                 i_target.getChildren<fapi2::TARGET_TYPE_CORE>
                 (fapi2::TARGET_STATE_FUNCTIONAL);
@@ -218,6 +223,30 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
                      "ERROR: Failed to set Fused core mode in PU_INT_TCTXT_CFG");
         }
 
+
+
+        // periodic core quiesce workaround settings
+        if (coreQuiesceDis == 1)
+        {
+            auto l_functional_core_vector =
+                i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+                (fapi2::TARGET_STATE_FUNCTIONAL);
+
+            for(auto l_chplt_trgt : l_functional_core_vector)
+            {
+                FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                                       l_chplt_trgt,
+                                       l_core_number),
+                         "ERROR: Failed to get the position of the CORE:0x%08X",
+                         l_chplt_trgt);
+                FAPI_DBG("CORE number = %d", l_core_number);
+
+                l_data64.flush<0>().setBit<p9hcd::CPPM_CPMMR_DISABLE_PERIODIC_CORE_QUIESCE>();
+                FAPI_TRY(fapi2::putScom(l_chplt_trgt, C_CPPM_CPMMR_OR, l_data64),
+                         "ERROR: Failed to assert CPMMR.core_periodic_quiesce_disable");
+            }
+        }
+
         // Initialize the PFET controllers
         FAPI_EXEC_HWP(fapi2::current_err, p9_pm_pfet_init, i_target, i_mode);